Mixed mode output buffer circuit for CMOSIC

Details Mixed mode output buffer circuit for CMOSIC Mixed mode output buffer circuit for CMOSIC

1995-08-07

1996-07-09

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 58, 326 83, 326 81, H03K 1716

Patent

active

055347894

ABSTRACT:
This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

REFERENCES:
patent: 4963766 (1990-10-01), Lundberg
patent: 5266849 (1993-11-01), Kitahara et al.
patent: 5338978 (1994-08-01), Larsen
patent: 5450025 (1995-09-01), Shay
patent: 5467031 (1995-11-01), Nguyen
patent: 5493233 (1996-02-01), Shigehara

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