Mixed mode erase method to improve flash eeprom write/erase thre

Details Mixed mode erase method to improve flash eeprom write/erase thre Mixed mode erase method to improve flash eeprom write/erase thre

1997-08-11

1999-01-19

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518519, 36518526, 36518527, G11C 1604

Patent

active

058620788

ABSTRACT:
A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to detrap the tunneling oxide of the flash EEPROM cell. The channel erasing consists floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a first relatively large negative voltage pulse is applied to the control gate, as a first moderately large positive voltage pulse is applied to said source. The method to erase then proceeds with the source erasing to remove charges from the floating gate of the flash EEPROM cell. The source erasing consists of applying a second relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a second moderately large positive voltage pulse to a first diffusion well. At the same time the ground reference potential continues to be applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float.

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