Mitigating silent data corruption in a buffered memory...

Details Mitigating silent data corruption in a buffered memory... Mitigating silent data corruption in a buffered memory...

Filed on

2005-06-24

Date issued

2010-06-08

Examiner

Torres, Joseph D (Department: 2112)

Patent Class

Error detection/correction and fault detection/recovery

SubClass

Pulse or data error handling

SubSubClass

Digital data error correction

Other Related Categories

C714S773000, C714S774000

Type

Reexamination Certificate

Status

active

Patent number

07734980

Description

ABSTRACT:
Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

REFERENCES:
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patent: RE34100 (1992-10-01), Hartness
patent: 5233614 (1993-08-01), Singh
patent: 5289478 (1994-02-01), Barlow et al.
patent: 5629948 (1997-05-01), Hagiwara et al.
patent: 6493843 (2002-12-01), Raynham
U.S. Appl. No. 10/456,353, filed Jun. 5, 2003, Vogt et al.
Vogt, “Fully-Buffered DIMM Technology Moves Enterprise Platforms to the Next Level” Technology@IntelMagazine Mar. 2005, p. 1-7.
Mukherjee, “The Soft Error Problem: An Architectural Perspective” IEEE 1530-0897-05 2005.

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