Miss tracking system and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395566, 711141, 711210, G06F 1202

Patent

active

057581789

ABSTRACT:
A miss tracking system optimizes the bandwidth to a main memory that is associated with a processor that utilizes a data cache and that executes instructions out of order. The miss tracking system includes the processor, the main memory in communication with the processor, and a data cache (DCACHE) associated with the processor. The processor has a memory queue (MQUEUE) for receiving and executing instructions that are directed to memory accesses to the DCACHE or the main memory. The MQUEUE includes a plurality of instruction processing mechanisms for receiving and executing respective memory instructions out of order. Each instruction processing mechanism includes an instruction register for storing an instruction and an address reorder buffer slot (ARBSLOT) for storing the data address of the instruction execution results. Significantly, dependent-on-miss (DM) indicator logic in each ARBSLOT prevents a request from its respective ARBSLOT to the main memory for miss data that is absent from the DCACHE when another ARBSLOT has already requested from the main memory the miss data. This is accomplished with DM indicator logic and a status indicator associated with each DCACHE data line. The DM indicator logic includes a DM indicator for asserting and deasserting a signal DM to indicate respectively whether or not an instruction associated with its respective ARBSLOT currently depends upon miss data that has not yet been received. The status indicator indicates a miss pending status, which means that the corresponding DCACHE data line is both invalid and has already been requested from the main memory.

REFERENCES:
patent: 5555392 (1996-09-01), Chaput et al.
patent: 5557769 (1996-09-01), Bailey et al.
patent: 5636364 (1997-06-01), Emma et al.
Anderson et al. Two Techniques for Improving Performance on bush-based Multiprocessors, Jan. 1995.
Carlton Multiple-Bus, Scalable-Memory Multiprocessors Chapter 5, 1992.
Johson Superscalar Microprocessor Design Chapter 8, 1991.
Goodman et al. The Wisconsin Multicarbes A New Large-Scale Caehe-Coherent Multiprocessor, 1988.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Miss tracking system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Miss tracking system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Miss tracking system and method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1977105

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.