Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-02
2002-03-26
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S413000
Reexamination Certificate
active
06362511
ABSTRACT:
BACKGROUND OF THE INVENTION
In the first place, a general process for manufacturing a MOS type integrated circuit, and more specifically, a process for manufacturing a CMOS-type integrated circuit will be explained with reference to
FIGS. 22A-22E
.
As shown in
FIG. 22A
, a device isolation insulating film
102
, an n-well
103
and a p-well
104
are first formed in a silicon substrate
101
.
Then, as shown in
FIG. 22B
, after a gate insulating film
105
is formed, a polycrystalline silicon film is deposited over the entire surface. Subsequently, the resultant structure is processed by optical lithography and anisotropic etching to form a gate electrode.
In general, the polycrystalline silicon film thus formed is constituted of columnar polycrystalline silicon having an average grain diameter of several tens nm, as viewed from above. In such a columnar polycrystalline silicon film, numerous small crystal grains are present at the interface with the gate oxide film
105
, as shown in FIG.
22
C. The sizes of the crystal grains increase as they go away from the interface.
As shown in
FIG. 22D
, to prevent an electric field from being converged at an edge of the gate electrode
106
, a post-oxidation film
107
is formed. Furthermore, impurity ions are doped at a level on the order of 1×10
13
-10
14
/cm
2
in the surface of the silicon substrate
101
by means of ion implantation. In this case, As
+
or P
+
is doped in an nMOSFET region and B
+
or BF
2
+
is doped in a pMOSFET region. In this manner, a so-called LDD region
108
(recently, sometimes called an “extension region”) is formed.
Then, as shown in
FIG. 22E
, a silicon nitride film or a silicon oxide film is deposited over the entire surface by a CVD method. The resultant structure is etch-backed to form a side-wall insulating film
109
on a side wall of the gate electrode
106
.
Furthermore, As
+
or P
+
is doped in the nMOSFET region and B
+
or BF
2
+
is doped in the pMOSFET region at a level on the order of 10
15
/cm
2
. After doped simultaneously in a source/drain region
110
and the gate electrode
106
as mentioned above, the impurity ions are electrically activated by high-temperature annealing such as RTA (Rapid Thermal Anneal).
Furthermore, for example, a CoSi
2
film
111
is formed on the source/drain region
110
and the gate electrode
106
to reduce resistance of the source/drain region
110
and the gate electrode
106
.
Thereafter, the resultant structure is subjected to usually-performed processes including an interlayer insulating film formation step, a metal wiring formation step, and a passivation film formation step. In this way, an LSI (not shown) is accomplished.
However, in the case where high integration and high performance of LSI are attained by using the aforementioned conventional techniques, the following problems are arisen.
The high integration and high performance of LSI are basically attained by reducing a gate channel length. However, it is not preferable to merely reduce the gate channel length since distribution of the electric field within the MOSFET is significantly changed, causing significant reduction in threshold voltage (short channel effect) and a reduction in punch-through voltage between the source and drain.
Accordingly, in practice, as the gate channel length is reduced, the gate insulating film and the depth of source/drain junction must be reduced in order to distribute the electric field almost uniformly within the MOSFET.
The source/drain junction depth can be generally reduced by suppressing the projection range by reducing the acceleration energy during the ion implantation and by performing the post annealing for a necessary and minimum time period. Since the impurity ions must be activated, a high-temperature/short-time annealing method, RTA, is generally performed after the ion implantation step. However, the junction depth has been shallower in recent years. In accordance with this tendency, the temperature and time of RTA have been reduced.
In these circumstances, a depletion phenomenon of the gate electrode has lately become a great matter of concern. The depletion phenomenon takes place when an energy band is bent at the interface between the gate electrode and the gate oxidation film and thereby a depletion layer is elongated (depletion). The depletion of the gate electrode is a phenomenon remarkably occurring when a density of electrically active impurity ions contained in the gate electrode near the interface with the gate oxidation film is low.
The depletion of the gate electrode is equivalent of reducing an effective capacitance of the gate oxide film, in other words, equivalent of increasing an effective film thickness of the gate oxide film.
The driving force for MOSFET can be expressed by a product of an activated carrier concentration and a carrier velocity. The activated carrier concentration is determined depending upon the effective capacitance of the gate oxidation film. Therefore, if the gate depletion occurs, the activated carrier concentration decreases. This directly means that the MOSFET driving force decreases.
The depletion of the gate electrode often and easily takes place when the gate electrode is formed of columnar polycrystalline silicon film and impurity ions are doped in the source/drain region and the gate electrode. This is because the impurity ions of the gate electrode are insufficiently activated since the annealing is performed at lower-temperature for shorter time, as the junction depth is reduced.
The reason why the impurity ions of the gate electrode are insufficiently activated, is as follows. Since the gate electrode is formed of the polycrystalline silicon film, grain boundaries are present in the gate electrode. The impurity ions of the gate electrode are usually segregated and inactivated in the grain boundary. The segregation/inactivation occurs more significantly as the temperature decreases. As a result, the impurity ions in the gate electrode are insufficiently activated as the temperature and time for the annealing are decreased, compared to that in the source/drain region.
Besides a lower activation rate at a certain temperature, there are another problem in that if later subjected to a step performed at 600 to 800° C. (e.g., interlayer insulating film deposition step), impurity ions once activated in the crystal grains are diffused to the grain boundary and then segregated and inactivated.
In fact, it has been experimentally confirmed that the depletion rate significantly changes when the gate electrode taken after completion of the interlayer film deposition step is compared to that taken after completion of the final step, as shown in FIG.
23
.
The segregation/inactivation readily occurs as the crystal grain is reduced in diameter and the grain boundary increased in number. Therefore, in the case, for example, a conventional case, where the columnar polycrystalline silicon film is used as the gate electrode, the number of the grain boundary increases near the interface between the gate electrode and the gate oxide film. As a result, in particular, the aforementioned segregation/inactivation problem easily occurs.
As is clear from the foregoing discussion, to solve the inactivation problem of impurity ions present in the gate electrode, it is better to increase the diameters of the crystal grains constituting the gate electrode (polycrystalline silicon film) because the grain boundary in the gate electrode reduces. However, the use of the polycrystalline silicon film having large-diameter grains (large-grain polycrystalline silicon film) produces the following new problems.
In general, the large-grain polycrystalline silicon film is formed by re-crystallization of an amorphous silicon film. However, in the recrystallization method, a single crystal is formed in the depth direction of the film, so that individual crystal planes differ in orientation (crystal axes), as shown in FIG.
24
.
When impurity ions are doped by ion implantation into the gate ele
Mizushima Ichiro
Takagi Mariko
Chaudhuri Olik
Finnegan Henderson Farbow Garrett & Dunner, L.L.P.
Kabushiki Kaisha Toshiba
Pham Hoai
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