Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – Field relief electrode
Reexamination Certificate
2001-02-27
2003-02-25
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
Field relief electrode
C257S490000
Reexamination Certificate
active
06525390
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices of MIS type (insulated gate type), such as a lateral power MOSFET, having a main current path in the lateral direction thereof. More specifically, the present invention relates to a semiconductor device structure that facilitates the stabilization of breakdown voltage of the semiconductor device and lowering the on-resistance thereof.
BACKGROUND
The so-called lateral power MOSFET, which has a main current path in the lateral direction thereof, is manufactured by planar diffusion from the surface of a semiconductor substrate. The lateral power MOSFET is characterized in that the lateral power MOSFET employs a reduced surface electric field (RESURF) technique and other such techniques to expand the depletion layer in the lateral direction thereof. This is caused by a reverse bias voltage applied between the source and the drain of the lateral power MOSFET, so that a certain breakdown voltage may be secured. Since the lateral power MOSFET is manufactured through a typical IC process, monolithic power IC's, having a control circuit and lateral power MOSFET's integrated therein, have been placed on the market.
FIG. 19
is a cross sectional view of a conventional n-channel lateral power MOSFET (hereinafter referred to as a “first conventional power MOSFET”) disclosed in U.S. Pat. No. 4,811,075. Referring to
FIG. 19
, the first conventional lateral power MOSFET includes a highly resistive p-type substrate
101
, having of resistivity is of about 125 ohm-cms; an n-type offset region
103
in the surface portion of p-type substrate
101
; a p-type base region
102
in the surface portion of p-type substrate
101
, base region
102
including (1) an n
+
-type source region
105
in the surface portion thereof and (2) a channel portion in the extended portion thereof, extending between source region
105
and n-type offset region
103
; a p-type offset region
104
in the surface portion of n-type offset region
103
, the potential of the p-type offset region
104
being fixed at the source potential; an n
+
-type drain region
106
in the surface portion of n-type offset region
103
, the n
+
-type drain region
106
being spaced apart from n
+
-type source region
105
for about
80
micrometers; a field oxide film
108
on p-type offset region
104
; a gate oxide film
107
on the channel portion of base region
102
; a gate electrode
109
on gate oxide film
107
; a source electrode
111
on source region
105
; a drain electrode
112
on drain region
106
; an interlayer film
113
; and a protection film
114
. The n-type offset region
103
is extended toward source region
105
. A p
+
-type region is disposed on base region
102
to secure ohmic contact for base region
102
.
When a reverse bias voltage is applied between source electrode
111
and drain electrode
112
, a depletion layer expands from the pn-junction between substrate
101
and n-type offset region
103
and another depletion layer from the pn-junction between n-type offset region
103
and p-type offset region
104
. The first conventional power MOSFET is configured such that two depletion layers expand in a well-balanced manner and join each other to relax the electric field and, thereby, to secure a high breakdown voltage. Equipotential curves at an applied voltage of 750 V are shown in
FIG. 19
, at intervals of every 150 V.
Usually, actual lateral power MOSFET products are packaged in a plastic mold. Ionic particles (ions
105
or electric charges) in the plastic mold of a lateral power MOSFET cause unfavorable phenomena as described below.
When high voltage is applied between the source and the drain of the lateral power MOSFET packaged in a plastic mold, especially at high temperatures, positive ions
115
a
and positive electric charges in the plastic mold are attracted toward source electrode
111
, and negative ions
115
b
and negative electric charges in the plastic mold are attracted toward drain electrode
112
. As a result, in the portion to which the positive ions
115
a
and positive electric charges are attracted, protection film
114
, interlayer film
113
and field oxide film
108
constitute a capacitor. On the substrate side thereof, negative electric charges
115
c
are induced, as shown in FIG.
20
. The induced negative electric charges
115
c
turn a part of p-type offset region
104
to an n-type. In the portion to which the negative ions
115
b
and negative electric charges are attracted, positive electric charges
115
d
are induced, as shown in FIG.
20
. The induced positive electric charges
115
d
thicken a portion of p-type offset region
104
. Therefore, the original p-type offset region
104
deforms to a p-type offset region
104
a
. The deformation of the p-type offset region
104
causes an imbalance between the expanding depletion layers, a strong electric field locally, and lowers the breakdown voltage between the source and the drain.
In the first conventional lateral power MOSFET of
FIG. 19
, the main current path between the source and the drain is n-type offset region
103
in the ON-state. However, since p-type offset region
104
is formed in the surface portion of n-type offset region
103
to promote depletion at reverse bias voltage application, the main current path is pinched off easily (JFET effect) as the drain voltage rises and, thereby, the on-resistance is increased.
FIG. 21
is a cross sectional view showing a second conventional lateral power MOSFET and equipotential curves therein. The second conventional lateral power MOSFET has a structure that omits the p-type offset region
104
from the first conventional lateral power MOSFET of FIG.
19
. Since there exits no p-type offset region in the second conventional lateral power MOSFET, the main current path thereof is hardly pinched off. As a result, the on-resistance thereof is suppressed at a low value. However, since a pn-junction is formed only between the p-type substrate and the n-type offset region, the n-type offset region is not easily depleted when a reverse bias voltage is applied. The breakdown voltage of the second conventional lateral power MOSFET is about 450 V, which is lower than that of the first conventional lateral power MOSFET.
Two problems of the conventional lateral power MOSFET's described above will now be summarized. First, when high voltage is applied at a high temperature between the source and the drain of the first conventional lateral power MOSFET packaged in a plastic mold, ions and electric charges in the plastic mold are attracted toward the source electrode and the drain electrode, and are localized thereon. The localized ions and electric charges induce electric charges of opposite polarities on the substrate side of the capacitor formed by the protection film and such other constituents. The induced electric charges deform the p-type offset region, cause an imbalance of depletion, and lower the breakdown voltage between the source and the drain.
Secondly, in the first conventional lateral power MOSFET, since the main current path in the ON-state is the n-type offset region between the p-type substrate and the p-type offset region, the main current path is easily pinched off as the drain voltage rises and the on-resistance is increased. In the second conventional lateral power MOSFET that omits the p-type offset region from the first conventional lateral power MOSFET, the n-type offset region is not easily depleted at reverse bias voltage application. Thus, the breakdown voltage is lowered.
In view of the foregoing, it is an object of the invention to provide a semiconductor device, manufactured at low manufacturing cost, that obviates the problems described above and prevents the lowering of the breakdown voltage.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor device having a MIS structure, the semiconductor device including: a semiconductor substrate of a first conductivity type; a b
Fujishima Naoto
Kitamura Akio
Saito Masaru
Tada Gen
Dickey Thomas L
Fuji Electric & Co., Ltd.
Rossi & Associates
Tran Minh Loan
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