Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-25
2004-06-01
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S346000, C257S387000, C257S408000, C257S900000
Reexamination Certificate
active
06744099
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
In general, the present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to enhancement of an operating current of a super-miniaturized MIS semiconductor device and super enhancement of an operating speed of the MIS semiconductor device.
2. Description of the Related Art
Enhancement of performance of an insulated-gate field-effect transistor or, in particular, a MIS field-effect transistor (hereinafter, simply abbreviated to MISFET) employed in a super-density semiconductor device is based on a scaling law and has been successful. The success of the enhancement of an insulated-gate field-effect transistor's performance is attributed to a decrease in applied power-supply voltage, a decrease in transistor area and miniaturization of gate dimensions. The decrease in transistor area and the miniaturization of gate dimensions should provide a merit of a decrease in parasitic capacitance.
If the gate dimensions are decreased, however, a short-channel effect is resulted in, causing a threshold voltage to fluctuate. In order to reduce the short-channel effect accompanying miniaturization of the length of the gate electrode in the super miniaturized MIS described above, an effort to make a junction of a source diffusion layer and a drain diffusion layer shallow is promoted.
Even in the case of a MISFET with a shallow junction of the source diffusion layer and the drain diffusion layer, as the device is miniaturized to reach a gate length equal to or smaller than 100 nm, it becomes difficult to assure a large effective channel length because of the existence of an overlap area between the gate and the source/drain diffusion layers and, hence, hard to suppress the short-channel effect. This overlap area is generated due to diffusion of impurities during a heat treatment carried out for the purpose of activating the impurities.
In order to solve the problems described above, in accordance with a typical solution disclosed in Japanese Patent Laid-open No. H7(1995)-245391, after a first side-wall spacer is provided on a side wall of the gate electrode, impurities are introduced with the gate electrode and the first side-wall spacer used as masks to form an N- or P-source diffusion layer area and a drain diffusion layer area. As a result, it is possible to form an effective structure in which a large effective gate length is assured.
In addition, in accordance with a disclosure described in Japanese Patent Laid-open No. H5(1993)-3206 as a typical means for suppressing an increase in source/drain parasitic resistance, a first side-wall spacer is used as a material with a dielectric constant greater than that of an oxide layer. In addition, an electric field in an N- or P-area of source/drain region at the gate edge is strengthened so as to reduce the resistance of a parasitic resistance under the first side-wall spacer. Thus, an effective result of an increased driving current can be obtained.
SUMMARY OF THE INVENTION
In the structure disclosed in Japanese Patent Laid-open No. Hei7-245391, the concentration of impurities in the N- or P-area of the gate edge is low in comparison with a concentration, which is obtained when a diffusion layer area is formed with only the ordinary gate electrode used as a mask. Thus, the resistance of a source/drain parasitic resistance increases, giving rise to a demerit of a deteriorating driving power.
In addition, the structure disclosed in Japanese Patent Laid-open No. Hei5-3206 is limited to an offset gate structure including a portion in which the gate electrode and the source/drain diffusion layer areas do not overlap each other.
In the case of the offset gate structure, a channel resistance of an offset area has a very high resistance value. Thus, even if a material having a high dielectric constant is used for making the first side-wall spacer, it is difficult to obtain a sufficient high driving current.
Furthermore, if all materials used for making the first side-wall spacer have a high dielectric constant as described above, the fringing capacitance of the gate will increase, raising a problem of an extremely long signal delay.
As described above, with the conventional technologies, it is difficult to suppress the short-channel effect and to assure a large driving current at the same time.
It is thus an object of the present invention addressing the problems described above to provide a MIS semiconductor device that is excellent in that the short-channel effect can be suppressed and, at the same time, a large driving current can be assured, and to provide a method of manufacturing the MIS semiconductor device. Further, it is an object of the present invention to provide a MIS semiconductor device and its manufacturing method which realize a reduction of the fringing capacitance of the gate and speeding-up of the signal delay.
The present invention is based on a result of a discovery of the new phenomenon in a study of an optimum condition for structures of a source region and a drain region in the MIS semiconductor device. Details of the present invention are described as follows.
FIG. 3
is a diagram showing changes in transistor driving current and transistor parasitic resistance, which were obtained by simulation when the relative dielectric constant of a dielectric used for making the first side-wall spacer was varied. The values are normalized on the basis of the value of a silicon-oxide film with a relative dielectric constant of 3.9. The larger becomes the relative dielectric constant, the smaller the parasitic resistance and, hence, the driving current becomes larger.
On the other hand,
FIG. 4
is a diagram showing changes in transistor delay and transistor parasitic capacitance, which were obtained when the relative dielectric constant of a dielectric used for making the first side-wall spacer was varied. The values are normalized on the basis of the value of a silicon-oxide film with a relative dielectric constant of 3.9 as is the case with the values shown in FIG.
3
. The larger the relative dielectric constant, the smaller the transistor delay. This is because, for a large relative dielectric constant, the effect of an increased driving current is greater than the effect of an increased parasitic capacitance value. That is, the larger becomes the relative dielectric constant of a dielectric used for making the first side-wall space, the higher the possibility of a high-speed operation of the transistor.
FIG. 5
is a diagram showing changes in driving current, which were obtained when the width of the first side-wall spacer was varied. The driving current increases as the width of the first side-wall spacer increases. As the width of the first side-wall spacer reaches a value close to 7 nm, the driving current reaches a maximum value. When the width of the first side-wall spacer is further increased, and it exceeds 15 nm, the driving current stays at a constant.
The present invention is based on a result of a discovery of the new phenomenon in a study of an optimum condition for structures of a source diffusion layer and a drain diffusion layer in the MIS semiconductor device.
In order to achieve the object described above, the present invention provides a MIS semiconductor device and a method of manufacturing the MIS semiconductor device.
The MIS semiconductor device provided by the present invention is characterized in that the MIS semiconductor device comprises:
a gate dielectric formed on a semiconductor substrate of a first conduction type;
a gate electrode provided on the top surface of the gate dielectric;
a first side-wall spacer formed in a state of being brought into contact with the surface of the semiconductor substrate spread over the side wall and outer circumference of the gate electrode;
a first impurity area formed by introduction of first impurities having a conduction type opposite to the first conduction type into the semiconductor substrate with the gate electrode and the first si
Horiuchi Masatada
Tsuchiya Ryuta
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Ngo Ngan V.
LandOfFree
MIS semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MIS semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MIS semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3364508