Electrical computers and digital processing systems: memory – Address formation – Using table
Reexamination Certificate
1999-11-26
2003-01-28
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Using table
C711S005000, C711S170000, C711S217000, C365S230030, C365S238500
Reexamination Certificate
active
06513106
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of solid state memory systems and more particularly to a method and circuit for implementing a hardware based mirror addressing mechanism.
2. Description of the Relevant Art
In the field of digital signal processing (DSP), it is not uncommon to encounter data structures that are characterized by recurring, repetitive, or cyclical values. Trigonometric functions, for example, are frequently implemented in DSP's by utilizing multiple entry data tables that contain values of a function at various input points. When the function is called by an application program, the input value in the function called is used to index the table. The value corresponding to the indexed entry is returned as the value for the function call. Because memory is precious, it is desirable to attempt to conserve memory space by eliminating redundant data values from a data table such that the data table contains only a single copy of the each value. In addition, it would be beneficial if the implemented solution for reducing the size of a symmetrically arranged data structure was transparent to the application programmer and did not measurably affect system performance.
SUMMARY OF THE INVENTION
A method and system for implementing a mirror addressing scheme in conjunction with a symmetrical data table are disclosed. The method includes receiving a first address. In response to determining that the first address corresponds to an upper portion of a data table, generating a second address from the first address, where the second address corresponds to a lower portion of the data table. The method further includes using the second memory address to access a memory array, whereby data corresponding to the upper portion of the data table is accessed from the lower portion of the data table. In one embodiment, determining that the first address corresponds to an upper portion of the data table is achieved by determining upper segment and lower segment boundaries for the first memory address determining that the most significant bit of the lower segment is asserted. Generating the second memory address from the first memory address may include complementing the lower segment of the first memory address and combining the complemented lower segment with the upper segment of the first memory address. In one embodiment, the method includes writing a buffer size register with a value indicative of the size of the number of entries in the symmetric data table. In this embodiment, determining the lower segment boundary may include determining the most significant bit of the buffer size register that is asserted. In alternative embodiments, complementing the lower segment address may comprise generating a 2's complement of the lower segment if the symmetry of the symmetric data table is odd and generating a 1's complement of the lower segment address if the symmetry of the data table is even.
The invention further contemplates an address generation unit, comprising a buffer size register suitable for indicating the size of a symmetric data table, a detection circuit adapted to determine whether a first address received by the data address generation circuit corresponds to an upper portion of the symmetric data table or a lower portion of the data table, and an address generator. The address generator is adapted to generate a second memory address from the first memory address if the detection circuit determines that the first address corresponds to the upper portion of the symmetric data table. In this manner, the second address corresponds to the lower portion of the data table such that data associated with the first address and its corresponding second address are stored in a common location. In one embodiment, the least significant N bits of the buffer size register are asserted to indicate a buffer size of 2
N
. In one embodiment, the detecting circuit determines the boundaries of an upper segment of the first memory address and a lower segment of the first address. The most significant asserted bit in the buffer size register may indicate an upper boundary of the lower segment. The address generator may generate a second address from the first address by complementing the lower segment of the first address and concatenating the complemented lower segment with the upper segment of the first address. The address generator may complement the lower segment in a 2's complement manner for a data table with odd symmetry and in a 1's complement manner for a data table with even symmetry.
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Lau Winnie
Perets Ronen
Chace Christian P.
Dewan & Lally, LLP
LSI Logic Corporation
Yoo Do Hyun
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