Minimum latency propagation of variable pulse width signals...

Details Minimum latency propagation of variable pulse width signals... Minimum latency propagation of variable pulse width signals...

2005-05-31

2005-05-31

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

C713S502000, C326S096000

Reexamination Certificate

active

06901528

ABSTRACT:
An apparatus comprising a counter circuit, a first register circuit, a second register circuit and an output circuit. The counter circuit may be configured to generate a count signal in response to a data input signal and a first clock signal operating in a first clock domain. The first register circuit may be configured to generate a first control signal in response to the count signal. The second register circuit may be configured to generate a second control signal in response to the data input signal. The output circuit may be configured to generate a data output signal operating in a second clock domain in response to the first control signal, the second control signal, the count signal, and a second clock signal.

REFERENCES:
patent: 6172538 (2001-01-01), Selwan
patent: 6260152 (2001-07-01), Cole et al.
patent: 6359479 (2002-03-01), Oprescu
patent: 6362668 (2002-03-01), Lutley et al.
patent: 6799280 (2004-09-01), Edenfield et al.

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