Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-02-28
2006-02-28
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S356000, C257S361000, C361S056000, C361S100000
Reexamination Certificate
active
07005708
ABSTRACT:
An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.
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patent: 6424013 (2002-07-01), Steinhoff et al.
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W. Wolf, Modern VLSI Design, 1994, PTR Prentice Hall, pp. 49 and 54.
Armer John
Jozwiak Phillip Czeslaw
Keppens Bart
Mergens Markus Paul Josef
Russ Cornelius Christian
Eckert George
Sarnoff Corporation
Sarnoff Europe
William J. Burke, Esq.
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