Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2011-05-03
2011-05-03
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S207000
Reexamination Certificate
active
07937556
ABSTRACT:
In one embodiment, a system comprises one or more registers configured to store a plurality of values that identify a virtual address space (collectively a tag), a translation lookaside buffer (TLB), and a control unit coupled to the TLB and the one or more registers. The control unit is configured to detect whether or not the tag has changed and in response to a change in the tag, map the changed tag to an identifier having fewer bits than the total number of bits in the tag, and provide the current identifier to the TLB. The TLB is configured to detect a hit/miss in response to the identifier. A similar method is also contemplated.
REFERENCES:
patent: 6510508 (2003-01-01), Zuraski, Jr. et al.
patent: 7293157 (2007-11-01), Parikh et al.
patent: 2006/0259734 (2006-11-01), Sheu et al.
patent: 2007/0061548 (2007-03-01), Jordan et al.
patent: 2007/0283125 (2007-12-01), Manczak et al.
Grohoski Gregory F.
Jordan Paul J.
Shah Manish K.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Nguyen Than
Oracle America Inc.
LandOfFree
Minimizing TLB comparison size does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Minimizing TLB comparison size, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimizing TLB comparison size will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2630045