Minimizing timing skew among chip level outputs for...

Details Minimizing timing skew among chip level outputs for... Minimizing timing skew among chip level outputs for...

2007-11-06

2007-11-06

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S037000, C326S039000, C326S040000, C326S093000, C326S095000, C326S098000, C326S112000, C326S119000, C326S121000, C716S030000, C327S208000, C327S224000, C327S225000

Reexamination Certificate

active

11278370

ABSTRACT:
A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.

REFERENCES:
patent: 5594367 (1997-01-01), Trimberger et al.
patent: 5811985 (1998-09-01), Trimberger et al.
patent: 6867615 (2005-03-01), Plants et al.
patent: 7218155 (2007-05-01), Chang et al.
patent: 7221193 (2007-05-01), Wang et al.

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