Minimizing signal stub length for high speed busses

Details Minimizing signal stub length for high speed busses Minimizing signal stub length for high speed busses

2000-03-17

2003-07-29

Dharia, Rupal (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C361S760000, C361S767000, C361S772000, C257S697000, C257S780000, C257S784000

Reexamination Certificate

active

06601125

ABSTRACT:

BACKGROUND OF THE INVENTION
The disclosed invention generally relates to digital computer bus systems, and more particularly to a bus conductor structure that significantly reduces signal stub length.
A digital computer system employs a multi-drop computer bus to communicate information between different components of the computer system. A computer bus is essentially a set of generally parallel electrically conductive signal lines or paths that communicate digital signals amongst different components of the computer system, and is commonly implemented as a plurality of generally parallel conductive traces supported by a printed circuit board.
FIG. 1
sets forth a schematic block diagram of a computer system that includes a main computer bus
11
and a secondary computer bus
12
. The main computer bus
11
is used, for example, for time critical functions such as high speed memory access, and connects a processor
13
to memory
14
and to various I/O interfaces
15
that in turn are connected to various I/O devices such as displays, keyboards, etc. The secondary computer bus
12
operates a slower speed than the primary computer bus
11
, and is used to accommodate slower I/O interfaces
16
. A bus controller
18
can be employed to couple the main computer bus
11
to the secondary bus
12
.
Each of the components connected to a multi-drop computer bus are implemented as one or more integrated circuits, wherein each integrated circuit is comprised of an integrated circuit package that houses an integrated circuit die and includes external electrical contacts on the outside of the package that are electrically connected to the integrated circuit die by conductive signal lines in the substrate of the package and wire bonds within the package. The external contacts are electrically coupled to respective computer bus signal lines by respective conductive lines formed in the circuit board that supports the computer bus. Thus, a wire bond, a package substrate based conductive line and a printed circuit board conductive line form a stub line that is a conductive signal path between a contact on an IC die and a computer bus signal path.
Signal transitions on a stub line cause reflections on the bus signal line to which it is connected, and as the operating frequency of a computer bus increases, reflections cause degradation of the signals on the computer bus lines. In other words, with increased operating frequency, reflections detrimentally impact the quality and integrity of signals on the computer bus.
There is accordingly a need for reducing reflections on a computer bus that are caused by connections to the bus.
SUMMARY OF THE INVENTION
The disclosed invention is directed to a computer bus that includes a conductive signal path comprised of a first conductive signal path in a printed circuit board, and a second conductive signal path in an integrated circuit package and electrically connected to said first conductive signal path, a third conductive signal path in the integrated circuit package, a fourth conductive signal path in the printed circuit board and electrically connected to said third conductive signal path, and circuitry electrically in the package electrically connecting said second conductive signal path and said third conductive signal path to a contact of an integrated circuit chip die contained in the integrated circuit package.


REFERENCES:
patent: 5266833 (1993-11-01), Capps
patent: 5982632 (1999-11-01), Mosley et al.
patent: 6008534 (1999-12-01), Fulcher
patent: 6064113 (2000-05-01), Kirkman
patent: 6091140 (2000-07-01), Toh et al.
patent: 6153829 (2000-11-01), Carapella et al.
patent: 6198635 (2001-03-01), Shenoy et al.
Pub. No. :US 2002/0033276 A1□□Dabral et al.□□Inline and “Y” Input-Output Bus Topology.*
Pub. No. :US 2002/0033276 A1, Dabral et al., Inline and “Y” Input-Output Bus Topology.

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