Minimizing path delay in a machine by compensation of timing thr

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364489, 364488, G06F 1560

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052375145

ABSTRACT:
A method for minimizing cycle time to improve machine performance is described. The approach prioritizes placement and partitioning decisions based on the criticality of paths and their constituent net segments. It provides an initial coarse approximation to a final more optimum configuration by iteratively improving on it through the use of deterministic techniques. The method optimizes placement by means of heuristic algorithms that are based on a cost function that is dependent on net segment and path criticality.

REFERENCES:
patent: 3654615 (1972-04-01), Freitag
patent: 4263651 (1981-04-01), Donath et al.
patent: 4495559 (1985-01-01), Gelatt et al.
patent: 4564943 (1986-01-01), Collins et al.
patent: 4615011 (1986-09-01), Linsker
patent: 4654851 (1987-05-01), Busby
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 4688947 (1987-08-01), Blaes et al.
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4787061 (1988-11-01), Nei et al.
patent: 4835705 (1989-05-01), Fujino et al.
"Circuit Placement for Predictable Performance" by Hange et al., IEEE 1987, pp. 88-91.
"Timing Influenced Layout Design" by Burstein et al., IEEE 22nd Design Automation Conf., 1985, pp. 124-130.
"Partitioning and Placement Technique for CMOS Gate Arrays" by Odawara et al., IEEE on C.A.D., vol. CAD-6, No. 3, May 1987, pp. 355-363.
"Analysis of Placement Procedures for VLSI Standard Cell Layout" by Hartoag, IEEE 23rd Design Automation Conf., 1986, pp. 314-319.
IEEE International Conference on Computer Aided Design, ICCAD-89 Digest of technical papers, 1988, pp. 52-5, entitled "Constrained Conditional Resource Sharing in Pipeline Synthesis".
VLSI Design, vol. 6, No. 2, Feb. 1985, pp. 86-91 entitled "Path-Delay Computation Algorithms for VLSI Systems".
IEEE Internatoinal Test Conference Proceedings 19-21 Nov. 1985, pp. 334-341 entitled "The Error Latency of Delay Faults in Combinations and Sequential Circuits".

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