Minimization of signal loss due to self-erase of imprinted data

Details Minimization of signal loss due to self-erase of imprinted data Minimization of signal loss due to self-erase of imprinted data

2007-10-16

2007-10-16

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S117000, C365S206000

Reexamination Certificate

active

11171663

ABSTRACT:
The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.

REFERENCES:
patent: 6157563 (2000-12-01), Hirano et al.
patent: 6922350 (2005-07-01), Coulson et al.
patent: 2005/0070032 (2005-03-01), Richards et al.
Coulson et al—U.S. Appl. No. 10/973,580, filed Oct. 25, 2004—Polymer De-Imprint Circuit Using Negative Voltage.

Affiliated with

Also associated with

Rating

Minimization of signal loss due to self-erase of imprinted data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Minimization of signal loss due to self-erase of imprinted data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimization of signal loss due to self-erase of imprinted data will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3885492