Minimization of microelectronic interconnect thickness...

Details Minimization of microelectronic interconnect thickness... Minimization of microelectronic interconnect thickness...

2005-04-19

2005-04-19

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06883153

ABSTRACT:
An efficient TCAD tool to analyze the variation of topography and thickness of interconnects and components of integrated circuits introduced by multiple-layer chemical-mechanical planarization (CMP). Contact stress distribution is determined on all scales as a function of topography. A formulation is used relating the pad deformation and therefore stress directly to pattern topography ({d}), and the pad mechanical properties. The 3-dimensional stress and deformation field is described, along with representation of the statistical pad roughness and slurry thickness information. These process conditions are also functions of the surface topography and contact regimes. The stress-topography relationship is represented as [A]{P}={d}, where [A] is the influence coefficient matrix determined by the contact mechanics, and {P} and {d} represent local stress and topography on patterns. With given initial topography and slurry rate kinetics, the surface evolution at each time step of CMP can be traced iteratively to obtain post-CMP topography.

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