Minimization of line width variation in photolithography

Details Minimization of line width variation in photolithography Minimization of line width variation in photolithography

1998-11-05

2001-02-13

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C257S435000, C257S437000, C148S033400, C438S744000

Reexamination Certificate

active

06187687

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and the fabrication of semiconductor devices and more particularly to process control of lithographic steps in semiconductor fabrication.
BACKGROUND
To achieve increased density and performance of VLSI (very large scale integrated circuits) integrated circuits, the characteristic size of features on those circuits is decreased. Fabrication of IC devices with features smaller than 0.18 &mgr;m, particularly fabrication of STI (shallow trench isolation) features, introduces new challenges in process development and control.
The process of making STI trenches typically involves a photolithographic step for patterning features in a photoresist layer overlying a silicon nitride (Si
3
N
4
) layer on a silicon substrate. In this process, dark and bright field features, i.e. thin lines and narrow spaces between structures or lines, are formed at the same time. As the characteristic size of lines and spaces becomes smaller, the acceptable tolerance in feature size variation also becomes smaller.
Variation in the width of the lines and spaces produced in the photoresist layer depends on the photolithographic process conditions, depth of focus and exposure, and on the variation in thickness of the photoresist and underlying silicon nitride layer. However, the lines and spaces do not respond in the same way to the process conditions. While these variations did not present a problem for older devices with larger feature sizes, for 0.18 &mgr;m scale devices, even with photoresist and Si
3
N
4
layer thickness variation kept to a practical minimum, the overlap in optimized process conditions to produce dark and bright field feature variations within acceptable tolerances is vanishingly small. Consequently, at the 0.18 &mgr;m scale, the photolithographic process may not be readily manufacturable.
The problem with variation in Si
3
N
4
thickness is that it leads to variation in substrate reflectivity which, in turn, results in line width variation. A typical stack formed in patterning an isolation structure is shown in
FIG. 1
a
where a patterned photoresist mask
22
overlays a Si
3
N
4
layer
18
in which a mask pattern is to be formed. An SiO
2
layer
14
is between the Si
3
N
4
layer
18
and the silicon substrate
10
. One solution to limiting line width variation is to introduce an organic anti-reflective coating (ARC)
20
between the photoresist and Si
3
N
4
18
layers to control substrate reflectivity, as shown in
FIG. 1
b.
However, there are contamination and defect problems associated with organic ARC's. Furthermore, organic ARC's significantly increase processing complexity because they require etching and stripping steps separate from those for Si
3
N
4
layers.
What is needed is a way to minimize line width variation to provide a manufacturable photolithographic process at the 0.18 &mgr;m scale without significantly increasing process complexity.
SUMMARY
According to the present invention, a practical photolithographic process for use in manufacturing isolation structures in integrated circuit devices at the 0.18 &mgr;m scale is provided. A silicon oxynitride layer introduced below a silicon nitride mask layer minimizes line width variation by minimizing substrate reflectivity. This reduction in line width variation allows greater latitude in specifying process conditions, such as exposure dose and focus, that pattern lines and spaces in the lithographic process within acceptable variations.
A method of using a silicon oxynitride ARC layer in forming isolation structures is also provided. First, a stack of layers is formed over a silicon substrate by conventional processes. The layers in the stack, from the top down, are: a photoresist layer, the silicon nitride mask layer, the silicon oxynitride ARC layer, and a silicon dioxide layer. Next, the photoresist layer is patterned by conventional exposure and development. Introduction of the silicon oxynitride ARC layer advantageously increases the exposure dose tolerance in the photolithographic process.
A plasma etch is performed to remove portions of the silicon nitride, silicon oxynitride, and silicon dioxide layers, and of the silicon substrate, underlying openings in the patterned photoresist layer. Because silicon oxynitride responds to the same etching conditions as silicon nitride, introduction of the silicon oxynitride ARC layer does not introduce any additional processing complexity.
A thin thermal oxide layer is grown in the etched opening. The silicon oxynitride layer provides the additional benefit of relieving edge/corner stress where the thermal oxide meets the silicon nitride layer, thus improving gate oxide integrity and reliability in a manufactured device of which the isolation structure forms a part.
The process of forming an isolation structure further includes depositing a silicon oxide layer over the thermal oxide, over which a patterned photoresist planarization mask is formed. The silicon oxynitride ARC layer also advantageously increases the tolerance on the process conditions for the patterning of the planarization mask.
Next, unprotected portions of the oxide layer are etched, followed by stripping of the photoresist, chemical mechanical polishing of the oxide, which is followed by chemical stripping of the silicon nitride and silicon oxynitride layer in a single process. The nitride and oxynitride layers both respond to the same chemistry.


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