Minimization-feasible word line structure for DRAM cell

Details Minimization-feasible word line structure for DRAM cell Minimization-feasible word line structure for DRAM cell

1999-08-23

2002-03-26

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S332000, C257S401000, C257S618000

Reexamination Certificate

active

06362506

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to dynamic random access memory (DRAM) cell devices and particularly relates to a minimization-feasible word line structure for such devices and a method of manufacturing the same.
BACKGROUND OF THE INVENTION
Continued growth in the capacity of dynamic random access memory (DRAM) technology can be enhanced by minimizing the size of individual DRAM cells. Such minimization has been hampered in prior devices and methods for a number of reasons. It has been difficult to fabricate prior devices with straight word lines; it has been difficult to maintain isolation when the DRAM cell size is reduced in cases where the bit line contact (BLCT) and storage node contact (SNCT) are not formed by a process which self-aligns them to the word lines; and it has been difficult to straighten both the active region and the bit lines at the same time in the cell over bit line (COB) type of cell.
In prior devices and methods, two typical structures have generally been employed in forming word lines for DRAM cells. In the first of these, the BLCT and the SNCT are not formed by a self-aligned process to the word lines. Such prior art structures are depicted in
FIGS. 1-4
. With reference to
FIG. 1
, a first prior art structure, designated generally as
10
, includes a plurality of substantially straight word lines
12
and a plurality of bit lines
14
orthogonal to the word lines
12
. The structure also includes a plurality of storage node contacts
16
, bit line contacts
18
, and active regions
20
. A cross section through structure
10
is depicted in FIG.
2
.
FIG. 2
shows the relationship of the word lines
12
, bit lines
14
, SNCTs
16
and BLCTs
18
to an insulator
22
and a LOCOS
24
. In viewing
FIG. 2
, it will be appreciated that the word lines
12
are not self-aligned to either the SNCTs
16
or the BLCTs
18
.
Still with reference to prior art structure
10
, the channel length L
g
of the transfer gate must be long enough in order to obtain a sufficient threshold voltage V
t
. Furthermore, sufficient space is required between the word lines
12
, BLCTs
18
and SNCTs
16
so that they do not touch each other. In order to meet these requirements, the length of a unit cell in the cross section perpendicular to the word lines had to become fairly large, thus impeding effective minimization of the structure. In an effort to overcome these problems, an alternative prior art structure, designated generally as
26
, was developed. Reference should now be had to
FIGS. 3 and 4
. As shown in
FIGS. 3 and 4
, the width of word lines
28
was widened at the transfer gate portion in order to meet the aforementioned requirements; conversely, the remainder of the word lines were narrowed since there was no need for greater width in those regions. This resulted in an irregular shape for the word lines
28
taken in plan view as shown in FIG.
3
and in turn caused large deformations of the actual word line patterns as compared to the mask patterns in the photolithography process. In turn, difficulty was encountered in keeping the width of the word lines
28
constant at the transfer gate portion, thus resulting in a large variation of the threshold voltage V
t
for the transfer gates. Further, since it was difficult to control the width of the word lines
28
due to the irregular shape, it was not practical to reduce cell size of the unit cell since the minimum stepper resolution could not be taken advantage of, as is the case for straight word lines.
Note that the remainder of the items depicted in
FIG. 3
, including the bit lines
14
, storage node contacts
16
, bit line contacts
18
and active regions
20
have all received the same numbering as in
FIGS. 1 and 2
.
FIGS. 9 and 10
depict another alternative to the prior art structure, which is designated generally as
30
. Word lines
12
, SNCTs
16
, active regions
20
, insulator
22
and LOCOS isolators
24
have received the same numbering as in FIG.
1
. Alternative structure
30
includes bit lines
32
and BLCTs
34
. It will be appreciated that in prior art structure
30
, a portion of the footprint of the BLCT
34
is placed over the isolation region. This can result in degradation of isolation performance between adjacent active regions or leakage from the BLCT
34
. The cause was etching off of a portion of the isolation region in the process of etching the hole for the BLCT
34
. It will be appreciated that similar problems would be encountered if modification was made to locate part of the SNCT footprint over the isolation region.
FIG. 11
depicts yet another prior art alternative to the structure
10
of
FIG. 1
, designated generally as
36
. The word lines
12
, SNCTs
16
and active regions
20
have received the same numbering as in FIG.
1
. Bit lines
38
are formed in a completely straight configuration, which is desirable. The BLCTs
40
cross over both the active region and the isolation region, in order to connect to the straight bit lines
38
, as depicted for the cell over bit line (COB) configuration of FIG.
11
. In theory, the configuration of
FIG. 11
can enable minimization of the length of the unit cell in the cross section parallel to the word lines
12
. However, in practice, similar problems w ere encountered to those discussed above for the configuration of
FIGS. 9 and 10
.
Reference should now be had to
FIGS. 5 and 6
which depict a prior art structure, designated generally as
42
, wherein the BLCTs
44
and SNCTs
46
are formed by a self-aligned process to the word lines
48
.
Structure
42
also includes bit lines
50
, LOCOS isolation structure
52
, and first and second insulators
54
,
56
respectively. It will be appreciated that the structure
42
permits use of straight word lines
48
and permits the word lines
48
to be self-aligned to the SNCT
46
and BLCT
44
. Unfortunately, the BLCTs
44
and SNCTs
46
, although they are self-aligned to the word lines
48
, are not self-aligned to the active region. Furthermore, the structure
42
exhibits many of the deficiencies discussed above for the structure
10
.
Prior art structures have generally employed two types of isolation. These are the LOCOS isolation method as depicted in FIG.
7
and the trench isolation method as depicted in FIG.
8
. As depicted in
FIG. 7
, in the LOCOS method, a plurality of LOCOS isolators
58
are embedded in the surface
60
of a substrate
62
and extend both inwardly and outwardly therefrom, with the active region
64
formed in between the LOCOS isolators
58
.
Reference should now be had to
FIG. 8
, which depicts a trench isolation structure. A plurality of trench insulators
66
are formed in a substrate
70
are flush with the surface
68
thereof. Active regions
72
are formed between trench insulators
66
.
The prior-art trench isolation method depicted in
FIG. 8
is prone to a problem with the characteristic of the source to drain current versus the gate voltage. Reference should now be had to
FIGS. 12A and 12B
, wherein the same reference characters as employed in
FIG. 8
are used. Also depicted are word line
74
, gate insulator
76
and corner regions
78
. A corner region
78
of the active region is formed at the boundary between the active region and the isolation region at trench insulator
66
. This occurs when the upper edge of the trench insulator
66
is located below the surface of the active region, as best seen in the detail of FIG.
12
B. In this case, an enhanced electric field results in the corner region
78
due to the gate being surrounded by the corner-shaped region. This in turn results in a “kink” on the order of double the threshold voltage V
t
in the characteristic source to drain current versus gate voltage. This was due to localized lowering of the threshold voltage V
t
in the corner region
78
.
SUMMARY OF THE INVENTION
Therefore, a need has arisen in the art for a word line structure for a DRAM cell which will permit effective minimization of the DRAM cell size with straight word lines, ef

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