Mini-batch process chamber

Details Mini-batch process chamber Mini-batch process chamber

1997-08-11

2002-03-05

Mills, Gregory (Department: 1763)

Coating apparatus

Gas or vapor deposition

With treating means

C118S641000, C118S725000, C118S730000

Reexamination Certificate

active

06352593

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process chamber capable of performing a variety of thermally driven processes and plasma enhanced processes, such as those involved in semiconductor wafer, flat panel display and hard disk manufacturing. More particularly, this invention relates to maintaining one or more rotating substrates within a controlled environment while injecting particular gases to produce the desired process results.
2. Brief Description of the Prior Art
There are a large number of processes that are performed at elevated temperatures inside of enclosed chambers (usually quartz furnace tubes) wherein the pressure, temperature and composition of gases are precisely controlled to produce the desired process results. Many of the processes performed in this fashion are similar for both semiconductor wafer and flat panel display manufacture and the fabrication of other devices on a wide variety of other substrates. For convenience, hereinafter the term wafer will be used with the understanding that the following would apply to the manufacture of flat panel displays and other types of substrates or devices wherein thermally driven (such as alloying, diffusion, annealing and glass reflow), CVD (Chemical Vapor Deposition) and/or PECVD (Plasma Enhanced Chemical Vapor Deposition) processes are employed.
For instance, silicon nitride is typically deposited on a wafers by CVD processing in a hot wall CVD reactor, as depicted in FIG.
1
and described by S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era, Volume 1—Process Technology”, Lattice Press, 1986, pp. 191-194. As shown in
FIG. 1
, a quartz-walled reactor
1
includes a quartz chamber
10
housing a boat
12
containing a plurality of wafers
14
which are heated by a furnace
16
having multiple zones of resistance heated elements
16
a
-
16
c
. Boat
12
typically contains between 80-150 of wafers
14
. A silicon nitride film is formed via chemical reaction on each of wafers
14
by injecting from tanks
17
gaseous silane or dichlorosilane and either nitrogen or ammonia into chamber
10
via an injection port
18
. Other films such as polysilicon, epitaxial silicon, metals, silicides, and glasses may be formed on wafers
14
in a similar fashion by injecting the appropriate reactant gases into the chamber. These reactant gases are removed from chamber
10
by an exhaust port
19
. Still other layers may be grown on the heated wafers such as silicon dioxide by injecting oxygen and/or water vapor into the chamber where the oxygen reacts directly with the surface of the silicon wafer to produce the SiO
2
.
Such a hot wall CVD chamber
10
, as illustrated in
FIG. 1
, is problematic for numerous reasons. First, during CVD processing of wafers
14
, the interior surface of the quartz walls of chamber
10
becomes sufficiently hot so as to enable the deposition of the reactant species thereon. As the deposited layer of reactant vapor becomes thicker, pieces thereof may flake off the quartz walls of chamber
10
and contaminate wafers
14
. Further, the formation of such a layer may deplete the reactant species such that little or no vapor deposition occurs on the wafers
14
. Consequently, the interior surface of the quartz walls of chamber
10
must be periodically cleaned, for example by using a wet etchant, which involves the complete removal of the quartz chamber from the furnace. Although some in the industry suggest alleviating this problem by positioning liners within chamber
10
, the liners are equally prone to flaking and must either be cleaned or replaced on a regular basis.
Note that as shown in
FIG. 1
, the reactant gases are typically injected into a first end of chamber
10
(via injection port
18
) and removed from another end of chamber
10
(via exhaust port
19
). As a result, the reactant gases are depleted as they travel through chamber
10
such that the deposition rate of the reactant vapor on those of wafers
14
proximate to injection port
18
is higher than those of wafers
14
proximate to exhaust port
19
. This phenomenon is known in the industry as the “gas depletion effect” and may result in unacceptable variations between films formed on the plurality of wafers
14
.
Another problem associated with hot wall CVD reactors such as reactor
1
is the significant time required both before and after processing of wafers
14
. Pre-processing time includes the time required to load the plurality of wafers
14
into boat
12
, insert boat
12
into chamber
10
, and slowly ramp up the temperature within chamber
10
from a loading/unloading temperature to a constant and uniform process temperature. Post-processing time includes the time required to slowly ramp the temperature down from the process temperature to the loading/unloading temperature, to remove boat
12
from chamber
10
, and to further cool boat
12
and wafers
14
therein to allow wafers
14
to be loaded into plastic wafer cassettes (not shown). The slow insertion rate of boat
12
into chamber
10
and removal rate of boat
12
from chamber
10
, as well as the slow temperature ramp up before processing and slow temperature ramp down after processing, are necessary to ensure minimal temperature gradients across the surface of wafers
14
, thereby avoiding wafer warping and/or crystal slippage of wafers
14
. While actual processing of wafers
14
may require only one-half hour, the time required for the pre- and post-processing procedures just discussed is typically 1 to 2½ hours. Accordingly, this pre- and post-processing time significantly limits the throughput of chamber
10
. Further, the slow temperature ramp up, the slow process of obtaining a uniform and constant temperature across the surface of wafers
14
, and the slow temperature ramp down result in chamber
10
contributing a relatively high thermal budget (the time that the wafers are above room temperature) to wafers
14
. As the size of semiconductor devices continues to decrease, it becomes increasingly important to minimize the thermal budget.
Although employing boat
12
capable of holding a large number of wafers helps to maximize throughput of chamber
10
, the simultaneous processing of so many of wafers
14
increases risk of wafer loss should something go wrong during processing. For instance, if a gas flow controller malfunctions or the vacuum pump ceases operating properly, all of wafers
14
in boat
12
may be destroyed.
Further note that where compatible process steps are to be performed on a wafer sequentially, it is often desirable to implement automated sequential processing in order to increase throughput. However, the relatively large size of chamber
10
and the large number of wafers
14
contained in boat
12
, coupled with the necessarily slow loading and unloading rate of boat
12
at atmospheric pressure, makes automated sequential processing in chamber
10
very cumbersome, if not impractical.
SUMMARY OF THE INVENTION
An improved reaction chamber is disclosed which overcomes problems in the prior art described above. In accordance with the present invention, the reactor includes a vacuum chamber having two distinct sections. The lower section is used for the loading and unloading of the wafers and the upper section is where the temperature, pressure and the flow of gases can be precisely controlled to produce desired uniform and consistent process results. The reactor is connected to a central transfer vacuum chamber via a slit valve such that the wafers can be loaded into the wafer boat while under vacuum via the robotic arm of the transfer chamber. The wafer boat is supported by a shaft which, being movable in a vertical direction, allows wafers to be loaded/unloaded into the various slots of the wafer boat. Once all the wafers are loaded into the boat, the slit valve is closed and the boat containing the wafers is elevated into the upper section of the chamber. The wafer boat and wafers therein are heated by multiple zone radiant heaters e.g. tungsten halogen lamps arrang

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