MIM formation method on CU damscene

Details MIM formation method on CU damscene MIM formation method on CU damscene

2001-11-01

2002-10-22

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S243000, C438S244000, C438S397000, C257S532000

Reexamination Certificate

active

06468873

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and manufacturing methods and systems thereof. More specifically, the present invention relates to metal-insulator-metal (MIM) structures and methods for forming such MIM structures. The present invention also relates to techniques for forming MIM structures in association with a damascene metal, such as copper.
BACKGROUND OF THE INVENTION
Recent efforts in miniaturizing ICs have focused on reducing the space consumed by the circuit components. The ongoing evolution in miniaturizing IC components has resulted in reduced costs and more circuit functionality for a given substrate size and manufacturing cost. For example, only a few years ago spacing between adjoining circuit elements in a typical IC was in the neighborhood of two to three microns. Today, many ICs are being designed at spacing distances as small as 0.35 microns or less. To accommodate narrower spacing, the electrical conductors are reduced in width. Increasing the thickness of the conductors to avoid degrading the quality of the signal conducted compensates for the reduction in width.
Increasing the thickness of the conductors also requires increases in the thickness of the dielectric insulation material, which separates and covers the conductors and components. The thickness of the dielectric must be greater than the height or topology difference among the components, to provide adequate insulation to separate the layers and components of the IC structure from one another. Increases in the thickness of the dielectric material are possible, in part, as a result of advanced planarization techniques such as chemical mechanical polishing (CMP). CMP smooths relatively significant variations in the height of the different components to a planar surface. Smoothing the variable-height topology to a planar surface allows the typical lithographic semiconductor fabrication techniques to be used to form considerably more layers than were previously possible in IC construction.
Excess conductive material on the surface of the dielectric layer can be typically removed by chemical mechanical polishing. One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques, for example, involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
In the semiconductor industry, ASIC memories have gained enormous popularity in integrated circuits (ICs) designs. ASICs allow custom or semi custom designs of ICs in shorter turn-around time while reducing the total component count and manufacturing costs. ASICs employ libraries of “standard cells” as building blocks to construct the desired logic circuits. Standard cells include commonly used programmable logic arrays, decoders, registers, counters, and other conventional circuits or components.
An ASIC chip contains single or multiple configurable memory arrays with row memory lines intersecting column memory lines. A plurality of column memory lines can be grouped together to form an I/O (input/output) memory block. In such instance, the memory array contains row memory lines intersecting I/O memory blocks. Each intersecting point between a row memory line and an I/O memory block represents one memory cell which stores a binary digit of logic “0” or “1”. The collection of these memory cells forms a memory array, which serves as a principle building block for implementing a custom or semi custom ASIC chip.
Because ASICs provide a truly cost-effective way of implementing a large number of digital logic circuits to perform a particular function, ASIC designers and IC fabricators have developed certain techniques for reducing the difficulty, expense and time required to design and debug an ASIC, and to manufacture the ASIC in quantity. Because experience has established that ASICs are cost-effective, the number of circuits included in and the complexity of ASIC designs increases year by year. Obviously, increasing ASIC complexity increases the likelihood of design errors in engineering prototypes, and also increases the number of iterations required to obtain a design that is commercially practical. Moreover, not only are ASIC designs becoming ever more complex, ASIC fabrication techniques are also advancing year by year.
MIM (Metal-Insulator Metal) structures have been widely used with ASIC products. MIM (Metal-Insulator-Metal) capacitors, for example, can be formed from a configuration in which a dielectric material is sandwiched between two metal electrodes. Known MIM devices, generally comprising a thin film insulating layer sandwiched between two conductive layers across which in use a voltage is applied, can be regarded as a kind of diode structure in that they exhibit a non-linear resistive characteristic and have been used in active matrix addressed liquid crystal display devices as switching elements in the addressing of the display device's picture elements. MIM structures are thus well known in the art.
Copper metallization of chips has thus been the subject of intense investigation for a number of years. Techniques for integrating MIM structures into copper damascene fabrication-based processes are essential for achieving widths in semiconductor processes of 0.13 um and beyond. One of the primary problems, however, in utilizing copper damascene fabrication-based techniques in association with the formation of MIM structures lies in the inability to avoid copper oxidation following a copper deposition and subsequent chemical mechanical polishing operations (CMP). Additionally, it is difficult using present fabrication techniques to achieve a uniform dielectric layer formed on metal layers of a MIM structure. The present inventors have thus concluded, based on the foregoing, that a need exists for a new semiconductor fabrication technique, including semiconductor devices thereof, which would produce a much more uniform dielectric layer in association with MIM structures, while simultaneously avoiding associated copper oxidation problems.
BRIEF SUMMARY OF THE INVENTION
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an improved semiconductor chip and associated circuitry thereof.
It is another aspect of the present invention to provide an improved MIM structure and formation methods thereof.
It is yet another aspect of the present invention to provide an improved MIM structure and methods for forming such a MIM structure into a copper damascene.
It is still another aspect of the present invention to provide improved MIM fabrication methods and devices thereof, which avoids copper oxidation problems.
It is another aspect of the present invention to provide improved MIM structure methods and devices thereof, which possesses highly uniform dielectric layers.
The above and other aspects of the present invention can be achieved as is now described. A method and apparatus for forming a metal-insulator-metal structure on a copper damascene, including a semiconductor device thereof, are disclosed herein. A copper layer may be initially deposited upon a substrate to form a copper damascene, wherein the copper layer forms a metal layer of a metal-insulator-structure. A barrier layer may then be formed upon the substrate following deposition of the copper layer upon the substrate. Thereafter, the copper layer can be polished utilizing chemical mechanical polishing (CMP) to provide enhanced uniformity of the copper layer, thereby p

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