Middle pull-up point-to-point transceiving bus structure

Details Middle pull-up point-to-point transceiving bus structure Middle pull-up point-to-point transceiving bus structure

2005-01-04

2005-01-04

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S027000, C326S086000, C326S021000, C327S108000, C327S098000

Reexamination Certificate

active

06838900

ABSTRACT:
A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

REFERENCES:
patent: 5731711 (1998-03-01), Gabara
patent: 5872471 (1999-02-01), Ishibashi et al.

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