Microwave field effect transistor structure

Details Microwave field effect transistor structure Microwave field effect transistor structure

2002-05-25

2004-12-14

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000, C257S408000, C257S409000, C257S488000

Reexamination Certificate

active

06831332

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is in the field of microwave field effect transistors, and more specifically, is in the field of a new Silicon power LDMOS structure optimized for operation above 3 GHz, for use in wireless communication applications.
2. Discussion of the Prior Art
In the prior art, power high frequency devices have been built using a variety of semiconductor technologies. For a long time the preferred vehicle for their realization has been the NPN bipolar junction transistor (BJT). Its primary advantage was the achievable high intrinsic transconductance (gm) that permitted the fabrication of high power devices utilizing small silicon areas.
As processing technology improved, in the early 1970's a number of MOSFET vertical structures began to challenge the dominance of the BJT at the lower RF frequencies, trading the cost of the large silicon area, necessary to provide the current capability in MOSFETs, for the cost of simple processing. The advantages that the MOSFET structure provided to the user were: higher power gain, ruggedness (defined as the capacity to withstand transients) and ease of biasing.
In the mid 1990's, new RF MOS devices that utilize the standard lateral MOS structure with a connection to the backside of the chip such that the back side becomes electrical and thermal ground, have extended the operational advantage of the MOSFET over the BJT into the 3 GHZ region thus covering three commercial bands of great importance: the cellular, PCS/PCN, and 3G mobile telephone bands. The concept of using the back side of the chip as an electrical and thermal ground was disclosed in the U.S. Pat. No. 5,949,104, issued to XEMOD, Inc.
As the applications for wireless communications move up in the frequency spectrum, parasitic resistances, capacitances and inductances limit the performance of the multiple conductive plug structure for lateral RF MOS devices, as described in the '104 patent.
What is needed is a new microwave transistor structure that has an improved performance due to the reduced parasitic gate-to-drain C
gd
capacitance, without impacting, in a deleterious manner, the other inter-electrode capacitances, including the gate-to-source C
gs
capacitance.
SUMMARY OF THE INVENTION
To address the shortcomings of the available art, the present invention provides a new microwave transistor structure that advances the frequency capabilities of the structure by diminishing the gate-to-drain C
gd
capacitance, without impacting, in a deleterious manner, the other inter-electrode capacitances, including the gate-to-source C
gs
capacitance.
One aspect of the present invention is directed to a microwave transistor structure. In one embodiment of the present invention, the microwave transistor structure comprises: (a) a substrate having a top surface; (b) a silicon semiconductor material of a first conductivity type including a first dopant concentration; the silicon semiconductor material is overlaying the top surface of the semiconductor substrate and has a top surface; (c) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (d) a channel region of the first conductivity type formed completely within the silicon semiconductor material including a channel dopant concentration; (e) a drain region of the second conductivity type formed in the silicon semiconductor material and contacting the channel region; (f) a body region of the first conductivity type and having a body region dopant concentration formed in the silicon semiconductor material under the conductive gate region, any remaining portion of the silicon semiconductor material underlying the gate is of the first conductivity type; (g) a source region of the second conductivity type and having a source region dopant concentration formed in the silicon semiconductor material within the body region; (h) a shield plate region being adjacent and being parallel to the drain region formed on the top surface of the silicon semiconductor material over a portion of the channel region; the shield region is adjacent and parallel to the conductive gate region; the shield plate extends above the top surface of the silicon semiconductor material to a shield plate height level, and is insulated from the top surface of the silicon semiconductor material; and (i) a conductive plug region formed in the body region of the silicon semiconductor material to connect a lateral surface of the body region to the top surface of the substrate.
In one embodiment of the present invention, the drain has a drain dopant concentration greater than the channel region dopant concentration. In one embodiment of the present invention, the body region dopant concentration is equal or greater than the first dopant concentration.
In one embodiment of the present invention, the channel region (d) further includes: (d
1
) a first enhanced drain drift region of the first conductivity type and having a first enhanced drain drift region dopant concentration; and (d
2
) a second enhanced drain drift region of the second conductivity type and having a second enhanced drain drift dopant concentration contacting the first drain drift region.
In one embodiment, the second enhanced drain drift dopant concentration is greater than the first enhanced drain drift region dopant concentration; and the drain region dopant concentration is greater than the second enhanced drain region dopant concentration.
In one embodiment, the microwave transistor structure of the present invention further includes a contact enhanced region of the first conductivity type located within the body region and having a contact enhanced region dopant concentration. In one embodiment, the contact enhanced region dopant concentration is greater than the body region dopant concentration.
In one embodiment, the conductive plug region further includes a conductive plug region formed in the contact enhanced region and the body region and connecting a top surface or a lateral surface of the contact enhanced region and a lateral surface of the body region to the top surface of the substrate. The conductive plug further comprises a metal plug, or a silicided plug. The silicided plug is selected from the group consisting of a tungsten silicided plug, a titanium silicided plug, a cobalt silicided plug, and a platinum silicided plug.
In one embodiment, the conductive gate further comprises a highly doped polysilicon gate. In another embodiment, the conductive gate further comprises a sandwich gate further comprising a highly doped polysilicon bottom layer and a top layer selected from the group consisting of a tungsten silicided, a titanium silicided, a cobalt silicided, and a platinum silicided.
In one embodiment, the shield plate region further includes a shield plate region connected to the source region. In an alternative embodiment of the present invention, the shield plate region further includes a shield plate region connected to a backside of the structure. The shield plate further comprises: a metal shield plate; or a polysilicon shield plate; or a polysilicon/silicided shield plate sandwich; or a polysilicon/metal shield plate sandwich.


REFERENCES:
patent: 5055896 (1991-10-01), Williams et al.
patent: 5252848 (1993-10-01), Adler et al.
patent: 5841166 (1998-11-01), D'Anna et al.
patent: 5907173 (1999-05-01), Kwon et al.
patent: 5949104 (1999-09-01), D'Anna et al.
patent: 6215152 (2001-04-01), Hebert
patent: 6521923 (2003-02-01), D'Anna et al.

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