Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-08-18
2002-04-30
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S763000
Reexamination Certificate
active
06380628
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits and, more specifically, to prevention of interlaminar de-lamination in chip wiring and packaging structures.
BACKGROUND OF THE INVENTION
Copper (Cu) is frequently used in chip wiring and packaging structures. Often, to prevent copper from contaminating the silicon or the dielectric in the device, a barrier layer is interposed between the silicon and the copper or between the dielectric and the copper. To maintain the structural integrity of the wiring structure, however, the adhesion between the barrier and dielectric and the barrier and the copper must be sufficient to survive subsequent processing.
Copper adheres poorly to most dielectrics and to some otherwise highly-desirable barrier films. As chip wiring ground rules continue to shrink, adhesion becomes an increasingly critical issue in chip fabrication, because the critical length for adequate adhesion and stress transfer within the wiring structure does not decrease monotonously with the dimensions of the lines and vias. For example, referring now to
FIGS. 1 and 2
, there are shown typical via and line structures of the prior art illustrating the critical parameters affecting adhesion.
Traditional fabrication processes for damascene structures, such as via
10
or line
20
, comprise first depositing a suitable photoresist material (not shown) on a substrate
12
, typically an insulator or dielectric such as an oxide, and then imaging the photoresist in a desired pattern of vias and lines. The photoresist image is then transferred onto substrate
12
by reactive ion etching (RIE) methods well known in the art. Via
10
and line
20
are then typically coated by a suitable barrier layer
14
, after which the structure is filled with a suitable metal
30
, such as copper, by electrodeposition, sputtering, or chemical vapor deposition (CVD) processes and the like, also well known in the art. Excess metal overburden (not shown) that may protrude above the surface
11
of substrate
12
, after the deposition step, may then be planarized to produce the finished structures as shown in
FIGS. 1 and 2
.
As shown in
FIGS. 1 and 2
, a cylindrical conductive via
10
in substrate
12
typically has a diameter d and a height h. Circular bottom
16
has an area A
b
and cylindrical wall
18
has a circumferential area A
c
. Thus, the surface areas of the interfaces between via
10
, barrier layer
14
, and substrate
12
can be expressed as follows:
A
b
=
1
4
π
d
2
(
1
)
A
c
=
π
d
h
(
2
)
A
c
A
b
=
4
h
d
(
3
)
When height h and diameter d are equal, i.e., when via
10
has an aspect ratio h/d equal to
1
, the ratio A
c
/A
b
is equal to 4. The ratio A
c
/A
b
thus increases linearly with an increase in aspect ratio.
Also shown in
FIGS. 1 and 2
, line
20
has a width W a depth D and a length L. The corresponding line floor
22
has an area A
f
and the total sidewall area A
w
comprises the sum of the areas of the four walls
23
and
24
as follows:
A
f
=WL
(4)
A
w
=2
WD+
2
DL
(5)
The corresponding ratio of line wall to floor area is thus:
A
w
A
f
=
2
WD
+
2
DL
WL
=
2
D
L
+
2
D
W
(
6
)
Because L is much greater than both Wand D, Equation 6 reduces to:
A
w
A
f
≅
2
D
W
(
7
)
Thus, for a line aspect ratio D/W equal to 1, A
w
/A
f
equals 2. As the line aspect ratio increases, A
w
/A
f
increases linearly.
FIG. 2
depicts the balance of stresses related to adhesion in via
10
. Tensile stress &sgr;
v
in force per unit area acting on conductive via
10
is opposed by adhesion stress &tgr;
v
in force per unit area such that:
σ
v
(
1
4
π
d
2
)
=
τ
v
(
π
dh
+
1
4
π
d
2
)
(
8
)
Equation 8 reduces to:
τ
v
=
σ
v
4
h
d
+
1
(
9
)
Thus, for an aspect ratio of 1, &tgr;
V
=&sgr;
V
/5.
Similarly, with respect to line
20
, tensile stress &sgr;
L
is opposed by adhesion stress &tgr;
L
such that:
&sgr;
L
WL=&tgr;
L
(
WL+
2
WD+
2
DL
) (10)
Equation 10 reduces to:
τ
L
=
σ
L
WL
WL
+
2
WD
+
2
DL
(
11
)
Again, because L>>D and L>>W, the following approximation may be used:
τ
L
=
σ
L
WL
WL
+
2
DL
=
σ
L
W
W
+
2
D
(
12
)
Thus, where the line aspect ratio equals 1 (i.e., W=D), then &tgr;
L
=&sgr;
L
/3.
If the adhesion stress &tgr;
V
exceeds the adhesion strength of any of the bonds between conductive via
10
, barrier layer
14
, and substrate
12
, de-lamination may ensue. Similarly, de-lamination may occur if &tgr;
L
exceeds the corresponding adhesion strength of any of the bonds between line
20
, barrier layer
14
, and substrate
12
. As described earlier, the adhesion strength of certain desired via and line materials, such as copper, to certain desired barrier layers or dielectrics may be relatively low. As the size of vias and lines are reduced, the surface area of the bonding surfaces also becomes reduced, whereas the adhesion strength and tensile stresses may be. the same. Hence, finer wiring structures may be exposed to increased interlaminar de-lamination or local separation of the dielectric or barrier layer from the metal structure of the vias or lines.
Thus, there is a need in the art for methods, structures, and processes of creating such structures to prevent interlaminar de-lamination.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides a damascene structure extending into an insulating substrate, the structure having a sidewall and a bottom, a liner on the sidewall and the bottom, and a conductive fill on the liner. The improvement comprises the liner having a roughened surface in contact with the conductive fill. The roughened liner surface may comprise a serrated pattern along a longitudinal section parallel to the substrate surface, and may further comprise a serrated pattern along a cross section intersecting the substrate surface. The damascene structure sidewall may also have a roughened surface in contact with the liner, in particular a roughened surface that comprises a serrated pattern along a longitudinal section parallel to the substrate surface. The liner may have a smooth surface over the damascene structure bottom, which may be smooth itself.
The invention also comprises a process for fabricating a conductive damascene structure in a substrate. The process comprises applying a photoresist over the top surface of a substrate and exposing the photoresist using exposure conditions that create a standing wave in the resist during resist exposure. Upon developing the photoresist, a damascene structure pattern is revealed having a plurality of serrations extending in a longitudinal plane substantially parallel to the substrate top surface. The pattern is transferred to the substrate to create in the pattern a damascene structure having a bottom and serrated sidewall with a plurality of serrations along a longitudinal section substantially parallel to the substrate top surface. A liner is applied over the bottom and over the sidewall in the substrate. The damascene structure is then filled with a conductive fill over the liner.
The liner may be applied over the sidewall in the substrate such that the liner surface has a plurality of serrations along a longitudinal section parallel to the substrate top surface. The liner may further be applied over the sidewall in the substrate such that the liner surface has a plurality of serrations along a cross-sectional plane intersecting the substrate top surface. The roughened surface may be achieved by applying a partial layer of liner material over the substrate, removing a portion of the partial layer, and repeating the application and removal steps until the liner sidewall conforms to the serrated sidewall in the substrate and has a sufficiently roughened surface
Miller John A.
Simon Andrew
Slattery Jill
Uzoh Cyprian E.
Wang Yun-Yu
Cao Phat X.
International Business Machines - Corporation
Ratner & Prestia
Townsend, Esq. Tiffany L.
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