Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-02-08
2002-06-25
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
06412057
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the internal configuration of a microprocessor which is able to read and write data more quickly than external memories.
BACKGROUND
A memory and I/O devices accessible to a processor are known as external devices. Because the memory is connected to almost all the processors, the memory is generally allocated directly to a memory map of the processors. On the other hand, because the I/O devices need a small address range, the I/O devices are typically managed by either of the following two methods.
(1) The I/O region is allocated to a specific memory space that the processor accesses with specific I/O instructions. For example, x86 processors of Intel Corp. have the I/O region other than an ordinary memory region, and the access to the I/O region is explicitly performed by in/out instruction.
(2) The I/O devices are allocated on a memory map of an ordinary main memory. For example, the processors based on a MIPS architecture access the I/O region by using the same instructions as those used for ordinary memory operations.
Recent processors have generally adopted the method (2) of the above-mentioned two methods. Because the method (2) can use the same instructions as those for ordinary access to the memory, the instruction set is simplified and programming is thus easier. However, when the processor accesses the I/O devices, it is necessary to use an accessing method which is different from that for the ordinary memory. Specifically, when the processor accesses the I/O devices, (i) the cache memory should not be used, (ii) the order of reading out from and writing into the I/O region should be assured.
Though many processors assure the order of reading out from and writing into the same address, in the case when a plurality of registers of one I/O device are allocated to a plurality of addresses, the order of reading out from and writing into the I/O region may not be assured.
As a result, a processor which performs “out-of-order” process interchanging, to interchange the order of executing instructions needs to be specifically addressed.
Furthermore, as a result of recent high-integration technique of the semiconductor and DRAM mixed technique, it is possible to accommodate a high-speed memory besides the cache memory inside the processor and to use this memory for a purpose which is different from the main memory or the cache memory.
However, if such high-speed memory is mapped to a portion of the memory space of the main memory, because the external memory and the I/O devices cannot be allocated to that mapped portion, the allocation of the memory map is restricted.
Furthermore, because the processor can access data on such kinds of the memory at high speed, if the data on such kind of the memory is registered with the cache memory, it may needlessly displace data caching causing the external memory to refill. Additionally, it requires an extra datapath to refill data from such kind of memory to the cache memory.
On the other hand, if the highs-speed memory contents are not cached, the kind of memory to be accessed, (that is, the high-speed memory or the cache memory) has to be automatically determined before such access.
SUMMARY
An object of the present invention is to provide a microprocessor comprising a RAM which is available for a purpose besides a cache memory, and which is able to access the RAM easily and at high speed.
In order to achieve the foregoing object, a microprocessor comprising:
a memory management unit for converting a virtual address to a physical address;
a load/store instruction executing block for executing a load/store instruction;
a RAM (Random Access Memory), from and to which said load/store instruction executing block is able to read and write data,
wherein said memory management unit includes a flag information generating block for generating a first flag information showing whether or not an access to said RAM is performed.
Because the processor according to the present invention determines by a first flag information whether or not the access to the RAM is performed, it is possible to access the RAM at high speed. That is, when accessing the memories, because it is unnecessary to refer to the result of “cache-hit” or “cache-miss”, it is possible to access the RAM without any additional delay to determine the destination of the memory access.
Furthermore, if such kind of the flag information is provided, because it is possible to access the above mentioned RAM by using the same instructions as those for the ordinary access to the memories, it is possible to simplify an instruction set and a programming model can be simplified.
Similarly, whether or not the access to an I/O region is performed is determined by a second flag information, it is therefore unnecessary to allocate a specific memory region for the I/O devices.
REFERENCES:
patent: 4654791 (1987-03-01), Ushiro
patent: 5606683 (1997-02-01), Riordan
patent: 5749093 (1998-05-01), Kobayashi et al.
patent: 5749094 (1998-05-01), Jaggar
patent: 5765194 (1998-06-01), McBride
Agarwal Rakesh
Malik Kamran
Raam Michael
Sasahara Masashi
Chace C. P.
Gray Cary Ware & Freidenrich LLP
Kim Matthew
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