Microprocessor with versatile addressing

Details Microprocessor with versatile addressing Microprocessor with versatile addressing

1997-09-26

1999-08-31

Donaghue, Larry D.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710129, 712 38, G06F 1338, G06F 1340

Patent

active

059448067

ABSTRACT:
A processor performs data transactions. For a first data transfer between the processor and a first external device which uses non-multiplexed data transactions, a first address is placed on an (external) address bus and first data is transferred on an (external) address/data bus. A second data transaction is performed between the processor and a second external device which uses multiplexed data transactions. In an address phase of the second data transaction, a second address is placed on the address/data bus. In a data phase of the second transaction, second data is transferred on the address/data bus.

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