Microprocessor with rate of instruction operation dependent upon

Details Microprocessor with rate of instruction operation dependent upon Microprocessor with rate of instruction operation dependent upon

1997-12-19

2000-10-24

Treat, William M.

Electrical computers and digital processing systems: processing

Processing control

Branching

713323, 713324, 713501, 713601, G06F 108, G06F 132, G06F 932

Patent

active

061382329

ABSTRACT:
A microprocessor operates at a rate dependent upon the interrupt source of a plurality of interrupt sources. The rate of power consumption by the microprocessor corresponds to the selected rate of instruction operation. A rate table accessed upon receipt of an interrupt stores a table of interrupt source to rate of instruction operation. The rate table may be a read only memory or a read/write memory loaded upon initiation of the microprocessor. The rate of microprocessor instruction operation may be set by frequency of an instruction clock or by a rate of instruction dispatch. For a superscalar microprocessor the rate of instruction operation may be set by setting a number of instructions dispatched per instruction cycle. On receiving an interrupt a rate number is pushed onto a rate stack. On return from the interrupt the rate stack is popped. The microprocessor operates at a rate corresponding to the rate number at a top of the rate stack. The invention may be coordinated with system management mode power control. A predetermined system management mode rate number is pushed onto the rate stack upon receipt of a system management interrupt entering the system management mode. The rate stack is popped upon exit from system management mode to normal mode.

REFERENCES:
patent: 4931748 (1990-06-01), McDermott et al.
patent: 5233314 (1993-08-01), McDermott et al.
patent: 5493684 (1996-02-01), Gephardt et al.
patent: 5719510 (1998-02-01), Weidner
patent: 5815693 (1998-09-01), McDermott et al.
patent: 5832280 (1998-11-01), Swanberg

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