Microprocessor with multiple supervisor interrupt processing fun

Details Microprocessor with multiple supervisor interrupt processing fun Microprocessor with multiple supervisor interrupt processing fun

1996-05-24

1997-12-23

Harvey, Jack B.

395733, G06F 946

Patent

active

057014949

ABSTRACT:
A microprocessor includes an interrupt request receiving circuit, a reception control section for controlling the interrupt request receiving circuit to receive an interrupt request in response to a reception control signal, and a control section for setting a supervisor interrupt mode when a supervisor interrupt request is received by the interrupt request receiving circuit in a state in which any supervisor interrupt request is not yet received. At that time, the reception control signal is issued to the reception control section such that the reception control section inhibits the interrupt request receiving circuit from receiving any supervisor interrupt request in the supervisor interrupt mode, and such that the reception control section permits the interrupt request receiving section to receive any user interrupt request in the supervisor interrupt mode. A user interrupt mode is set when a user interrupt request is received by the interrupt request receiving circuit in the supervisor interrupt mode. In the user interrupt mode, the reception control signal is issued to the reception control section such that the reception control section permits the interrupt request receiving circuit to receive any supervisor interrupt request and another user interrupt request in the user interrupt mode.

REFERENCES:
patent: 4727480 (1988-02-01), Albright et al.
patent: 5222215 (1993-06-01), Chou et al.
patent: 5438677 (1995-08-01), Adams et al.
patent: 5530874 (1996-06-01), Emery et al.

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