Microprocessor with microinstruction-specifiable...

Details Microprocessor with microinstruction-specifiable... Microprocessor with microinstruction-specifiable...

2009-05-20

2011-11-29

Faherty, Corey S (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S236000

Reexamination Certificate

active

08069339

ABSTRACT:
A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.

REFERENCES:
patent: 5440702 (1995-08-01), Brewer et al.
patent: 5551051 (1996-08-01), Silverthorn et al.
patent: 6629235 (2003-09-01), Flachs et al.
patent: 6684323 (2004-01-01), Soni
patent: 2002/0194458 (2002-12-01), Soni

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