Microprocessor with integrated high speed memory

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S024000

Reexamination Certificate

active

07747843

ABSTRACT:
A computer system with a processor architecture having more than one execution channel is described. The processor architecture contains at least one load/store unit for loading and storing data objects, and at least one data cache memory associated to the processor holding data objects accessed by the processor. The processor's load/store unit includes a load/store memory directly interfacing the load/store unit to the data cache.

REFERENCES:
patent: 4791550 (1988-12-01), Stevenson et al.
patent: 4907192 (1990-03-01), Kaneko
patent: 5072364 (1991-12-01), Jardine et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5761706 (1998-06-01), Kessler et al.
patent: 5793661 (1998-08-01), Dulong et al.
patent: 5887183 (1999-03-01), Agarwal et al.
patent: 5895501 (1999-04-01), Smith
patent: 5940876 (1999-08-01), Pickett
patent: 5996069 (1999-11-01), Yasoshima et al.
patent: 6237079 (2001-05-01), Stoney
patent: 6311260 (2001-10-01), Stone et al.
patent: 6530012 (2003-03-01), Wilson
patent: 6553486 (2003-04-01), Ansari
patent: 6571318 (2003-05-01), Sander et al.
patent: 6789171 (2004-09-01), Desai et al.
patent: 6918031 (2005-07-01), Wilson
patent: 6976147 (2005-12-01), Isaac et al.
patent: 7093103 (2006-08-01), Isomura
patent: 7174434 (2007-02-01), Blumrich et al.
patent: 7216218 (2007-05-01), Wilson
patent: 7346763 (2008-03-01), Wilson
patent: 2003/0074530 (2003-04-01), Mahalingaiah et al.
patent: 2003/0074544 (2003-04-01), Wilson
patent: 2003/0159023 (2003-08-01), Barlow et al.
patent: 2004/0250090 (2004-12-01), Crispin et al.
patent: 2005/0198478 (2005-09-01), Wilson
patent: 2005/0273576 (2005-12-01), Wilson
patent: 2005/0273582 (2005-12-01), Wilson
patent: 2007/0214319 (2007-09-01), Wilson
Hennessy et al.; “Computer Architecture: A Quantitative Approach”; 2nd Ed.; 1996; pp. 416-422.
“Advanced Computer Architectures”; Sima et al.; 1997; Addison-Wesley; p. 89-95, 175-179.
Non-Final Rejection mailed Jun. 26, 2006 for U.S. Appl. No. 10/857,843, filed Jun. 2, 2004, 17 pgs.
Notice of Allowance mailed Jan. 5, 2007 for U.S. Appl. No. 10/857,843, filed Jun. 2, 2004, 8 pgs.
Non-Final Rejection mailed May 5, 2006 for U.S. Appl. No. 10/857,964, filed Jun. 2, 2004, 18 pgs.
Final Rejection mailed Jan. 29, 2007 for U.S. Appl. No. 10/857,964, filed Jun. 2, 2004, 13 pgs.
Notice of Allowance mailed Oct. 23, 2007 for U.S. Appl. No. 10/857,964, filed Jun. 2, 2004, 7 pgs.
Non-Final Rejection mailed Dec. 10, 2007 for U.S. Application No. 11/797,754, filed May 7, 2007, 11 pgs.
Final Rejection mailed Dec. 8, 2008 for U.S. Appl. No. 11/797,754, filed May 7, 2007, 9 pgs.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Microprocessor with integrated high speed memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprocessor with integrated high speed memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor with integrated high speed memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4194542

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.