Microprocessor with improved performance during P-state...

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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C713S300000, C713S310000, C713S320000, C713S321000, C713S323000, C713S324000, C702S106000, C702S107000, C365S226000, C365S227000

Reexamination Certificate

active

07770042

ABSTRACT:
A microprocessor includes core logic that operates according to a core clock signal in order to execute program instructions, clock generation circuitry controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two, and a control circuit. The control circuit, in response to a request to operate the core logic at a destination frequency, iteratively controls the clock generation circuitry to generate the core clock signal having a new frequency until the core clock signal frequency is the destination frequency. The new core clock signal frequency on each iteration is one of the N different possible frequencies monotonically closer to the destination frequency. The number of iterations is between zero and N−1 depending upon the destination frequency specified and the core clock signal frequency when the request is received.

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