Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-02-13
2007-02-13
Padmanarhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S213000, C711S204000, C712S207000, C712S237000
Reexamination Certificate
active
10449825
ABSTRACT:
A microprocessor with multiple stream prefetch engines each executing a stream prefetch instruction to prefetch a complex data stream specified by the instruction in a manner synchronized with program execution of loads from the stream is provided. The stream prefetch engine stays at least a fetch-ahead distance (specified in the instruction) ahead of the program loads, which may randomly access the stream. The instruction specifies a level in the cache hierarchy to prefetch into, a locality indicator to specify the urgency and ephemerality of the stream, a stream prefetch priority, a TLB miss policy, a page fault miss policy, a protection violation policy, and a hysteresis value, specifying a minimum number of bytes to prefetch when the stream prefetch engine resumes prefetching. The memory subsystem includes a separate TLB for stream prefetches; or a joint TLB backing the stream prefetch TLB and load/store TLB; or a separate TLB for each prefetch engine.
REFERENCES:
patent: 5375216 (1994-12-01), Moyer et al.
patent: 5732242 (1998-03-01), Mowry
patent: 6128703 (2000-10-01), Bourekas et al.
patent: 6202130 (2001-03-01), Scales et al.
patent: 6240488 (2001-05-01), Mowry
patent: 6401192 (2002-06-01), Schroter et al.
patent: 6434649 (2002-08-01), Baker et al.
patent: 6785772 (2004-08-01), Venkumahanti et al.
patent: 2004/0186960 (2004-09-01), Poggio
Pieter Struik, Pieter Van Der Wolf, and Andy D. Pimentel; “A Combined Hardware/Software Solution for Stream Prefetching in Multimedia Applications”; Philips Research Laboratories.
Steve Vanderwiel, David J. Lilja; “A Survey of Data Prefetching Techniques”; University of Minnesota.
Sally A. Mc Kee, Robert H. Klenke, Kenneth L. Wright, William A. Wulf, Maximo H. Salinas, James H. Aylor, Alan P. Batson; “Smarter Memory: Improving Bandwidth for Streamed References”; IEEE 1998.
Steven P. Vanderwiel, David J. Lilja; “When Caches Aren't Enough: Data Prefetching Techniques”; University of Minnesota; IEEE 1997.
IA-32 Intel Architecture Software Developer's Manual-vol. 2: Instruction Set Reference-2001, pp. 3-600 through 3-601.
Keith Diefendorff, Michael Allen; Organization of the Motorola 88110 Superscalar RISC Mictroprocessor; IEEE 1992.
Keith Diefendorff, Rich Oehler, Ron Hochsprung; Evolution of the PowerPC Architecture; IEEEE 1994.
Stuart Ball, Robert Probin; “An Overview of AltiVec on the PowerPC”; 1998 Lightsoft.
AltiVec Technology Programming Environments Manual; Digital DNA From Motorola Feb. 2002.
AltiVec; The Caches; Memory and Alignment.
Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung, Hunter Scales; “AltiVec Extension to PowerPC Accelerates Media Processing”; IEEE 2000.
Ian Ollmann; “AltiVec (A.K.A. Velocity Engine)”; AltiVec Tutorial.
Davis E. Alan
Huffman James W.
MIPS Technologies Inc.
Padmanarhan Mano
Song Jasmine
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