Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1997-05-02
2001-05-08
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C712S219000
Reexamination Certificate
active
06230278
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to the field of electronic systems and more particularly to an improved modular audio data processing architecture and method of operation.
BACKGROUND OF THE INVENTION
Audio and video data compression for digital transmission of information will soon be used in large scale transmission systems for television and radio broadcasts as well as for encoding and playback of audio and video from such media as digital compact cassette and minidisc.
The Motion Pictures Expert Group (MPEG) has promulgated the MPEG audio and video standards for compression and decompression algorithms to be used in the digital transmission and receipt of audio and video broadcasts in ISO-11172 (hereinafter the “MPEG Standard”). The MPEG Standard provides for the efficient compression of data according to an established psychoacoustic model to enable real time transmission, decompression and broadcast of CD-quality sound and video images. The MPEG standard has gained wide acceptance in satellite broadcasting, CD-ROM publishing, and DAB. The MPEG Standard is useful in a variety of products including digital compact cassette decoders and encoders, and minidisc decoders and encoders, for example. In addition, other audio standards, such as the Dolby AC-3 standard, involve the encoding and decoding of audio and video data transmitted in digital format.
The AC-3 standard has been adopted for use on laser disc, digital video disk (DVD), the US ATV system, and some emerging digital cable systems. The two standards potentially have a large overlap of application areas.
Both of the standards are capable of carrying up to five full channels plus one bass channel, referred to as “5.1 channels,” of audio data and incorporate a number of variants including sampling frequencies, bit rates, speaker configurations, and a variety of control features. However, the standards differ in their bit allocation algorithms, transform length, control feature sets, and syntax formats.
Both of the compression standards are based on psycho-acoustics of the human perception system. The input digital audio signals are split into frequency subbands using an analysis filter bank. The subband filter outputs are then downsampled and quantized using dynamic bit allocation in such a way that the quantization noise is masked by the sound and remains imperceptible. These quantized and coded samples are then packed into audio frames that conform to the respective standard's formatting requirements. For a 5.1 channel system, high quality audio can be obtained for compression ratio in the range of 10:1.
The transmission of compressed digital data uses a data stream that may be received and processed at rates up to 15 megabits per second or higher. Prior systems that have been used to implement the MPEG decompression operation and other digital compression and decompression operations have required expensive digital signal processors and extensive support memory. Other architectures have involved large amounts of dedicated circuitry that are not easily adapted to new digital data compression or decompression applications.
An object of the present invention is provide an improved apparatus and methods of processing MPEG, AC-3 or other streams of data.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
SUMMARY OF THE INVENTION
In general, and in a form of the present invention a data processing device is provided that has a plurality of processing units wherein each of the processing units has an associated instruction memory and wherein each of the processing units is operable to execute instructions retrieved from the respective associated instruction memory simultaneously. A data bus is connected to each of the plurality of processing units and to a memory circuit, and the data is bus operable to transfer data between each of the plurality of processing units and the memory circuit, such that a first of the plurality of processing units is operable to store a first data word in the memory circuit and a second of the plurality of processing units is operable to read the first data word from the memory circuit. There is a first instruction sequencer in the first processing unit and a second instruction sequencer in the second processing unit. There is also instruction interconnect circuitry that is operable to transfer a first instruction directive from the first instruction sequencer to the second instruction sequencer The second instruction sequencer in the second processing unit is operable to begin processing a first sequence of instructions selected from the associated instruction memory in response to the first instruction directive.
In another form of the present invention, signaling means are provided for informing the first processing unit that the second processing unit has completed the first predetermined instruction sequence.
In another form of the present invention, the first instruction sequencer in the first processing unit is operable to execute an instruction from the associated instruction memory by sending a second instruction directive to the second instruction sequencer and by controlling a first data interconnect circuit and a second data interconnect circuit such that the second arithmetic circuit operationally replaces the first arithmetic circuit.
In another form of the present invention, a power control circuit is provided that is operational to cause the second processing unit to enter a low power mode in response to a predetermined instruction decoded by the second instruction sequencer. The power control circuit is also operational to restore the second processing unit to a full power mode in response to detecting the first instruction directive.
Other embodiments of the present invention will be evident from the description and drawings.
REFERENCES:
patent: 5155816 (1992-10-01), Kohn
patent: 5392437 (1995-02-01), Matter et al.
patent: 5649138 (1997-07-01), Ireton
patent: 5721945 (1998-02-01), Mills et al.
patent: 5734913 (1998-03-01), Iwamura et al.
MPEG-1, 3-11172.
MPEG-2,Information Technology—Generic Coding of Moving Pictures and Audio: Audio ISO/IEC 13818-3,2ndEdition, Feb. 20, 1997 (ISO/IEC JTC1/SC29/WG11 N1519), Int'l Org. for Standardisation Coding of Moving Pictures and Audio.
Digital Audio Compression Standard(AC-3), Dec., 20, 1995, Advanced Television Systems Committee, ATSC Standard.
TI-17424A (S.N. 08/475,251), allowed,Integrated Audio Decoder System and Method of Operation.
TI-17600 (S.N. 08/054,127), allowed,System Decoder Circuit With Temporary Bit Storage and Method of Operation.
TI-24442P (S.N. 60/030,106), filed Provisionally Nov. 1, 1996.Integrated Audio/Video Decoder Circuitry.
Gill Maria B. H.
Kam David (Shiu W.)
Laczko, Sr. Frank L.
Li Stephen (Hsiao Yi)
Ng Fuk Ho Pius
Brady III W. James
Laws Gerald E.
Niebling John F.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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