Microprocessor with arithmetic processing units and arithmetic e

Details Microprocessor with arithmetic processing units and arithmetic e Microprocessor with arithmetic processing units and arithmetic e

1998-06-17

2000-05-16

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

712206, 712203, 712 23, 708524, G06F 9302, G06F 938

Patent

active

060651121

ABSTRACT:
Along with an arithmetic processing unit and an arithmetic execution unit, another arithmetic processing unit is coupled in parallel to an instruction issue unit. Disposed within one of the arithmetic processing units are an address generation unit, an instruction buffer, an instruction decoder, an arithmetic execution unit, a data memory, and a flag register. The instruction decoder decodes an instruction read from the instruction buffer. If the decoded instruction is an iteration start instruction, the instruction decoder extracts a number of times an iterative process is to be executed that is included in the instruction for forwarding to the address generation unit. The address generation unit exerts control as to the execution and termination of iterative processes.

REFERENCES:
patent: 5404469 (1995-04-01), Chung et al.
patent: 5805913 (1998-09-01), Guttag et al.

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