Microprocessor unit for use in an indefinitely extensible chain

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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Details

710131, 710 38, 712 11, 712 16, 712 29, G06F 1337, G06F 1342

Patent

active

060214538

ABSTRACT:
A novel architecture is based on a general purpose microcomputer with an "upstream" bus and a "downstream" bus. The upstream bus interfaces to an integrated multiport RAM that is shared between an upstream processor and the local processor, and possesses both upstream and local (downstream) interrupts associated with dedicated locations in RAM. The upstream bus can be operated in two modes, a standard (EISA) PC bus MASTER mode in which the dual port RAM is compatible with an IBM PC bus and a SLAVE mode in which the upstream bus is compatible with the downstream bus. An indefinitely long chain of such processors can be initialized by one host. Orthogonal channels (decoupled from the main upstream/downstream bus) can be used to achieve unique functionality based on host control of arrays of such processors.

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