Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-06-01
2001-07-17
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S002000, C711S004000, C711S005000, C711S102000, C711S104000, C711S105000
Reexamination Certificate
active
06263399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for interfacing memory to a microprocessor. More particularly, the invention relates to an apparatus for interfacing NAND Flash memory to a microprocessor.
2. The Background Art
Most microprocessors, called Central Processing Units (CPU's), have a memory interface that they use to access conventional non-volatile memory e.g. ROM, Flash memory. Depending on the tasks the CPU is required to perform, the data stored in this non-volatile memory may include instructions to allocate RAM memory for system functions, or cause other system components to be put into a known state so that the all system components may be synchronized. If the system containing the CPU is designed to operate without external storage such as a hard drive or CDROM, the non-volatile memory may include operating system or application software. The size of the required non-volatile memory for any given system may range from a few kilobytes to several megabytes or larger, depending on the requirements of the particular system.
FIG. 1
depicts a prior art data processing apparatus.
Referring to
FIG. 1
, CPU
10
interfaces with memory
12
using chip select line
14
, output enable line
16
, read/write line
18
, address lines
20
, and data lines
22
. Chip select line
14
, output enable line
16
, and read/write line
18
may be grouped and classified as control lines, since they perform various control functions to ensure that the memory and the microprocessor are simultaneously ready for data transfers into or out of memory.
Some types of memory
12
have a single read/write line
18
which might be raised to a high logic level when a read operation is intended and held at a low when a write operation is intended. Other memories having a single read/write line may require a logical high be asserted when writing and a logical low be asserted when reading. A third type of memory might have two lines, a read enable line which is raised to a logical high when a read operation is intended, and a write enable line which is raised to a logical high when a write operation is intended. Read/write line
18
is intended to represent situations involving either a single read/write line, or involving separate read enable and write enable lines.
When CPU
10
has a need to read information from or write information to memory
12
, CPU
10
provides a memory address over address lines
20
, sets the proper condition of read/write line
18
, and then raises the output enable line
16
high. The data is then transferred between CPU
10
and memory
12
on data lines
22
.
Although this prior art apparatus is useful for its intended purposes, it suffers from the drawback that the maximum memory size is permanently fixed when CPU
10
and memory
12
are designed into a circuit. For a given size of memory a local bus having a certain number of address lines is required, with each address line being simultaneously asserted or deasserted, depending on the binary address of the memory cell being accessed. For example, in order to interface to a 16 KByte ROM, CPU
10
and memory
12
must have fifteen address lines. Once that design is fixed with a particular number of required address lines, there can be no increase in the amount of memory used in the particular design. In our example where the design was finalized as having a 16 Kbyte ROM memory, there would be fifteen address lines leading from the CPU to that ROM memory. If a later need arises for a larger ROM size, costly redesign must take place to add the required additional address lines to the local bus.
It would therefore be beneficial to provide a CPU-memory combination which allows for expansion of memory without having to redesign the surrounding circuitry.
Another drawback of the prior art system is the cost of the available memory. In common use today is conventional flash memory. The present invention provides an apparatus which, in a preferred embodiment, uses NAND flash memory which provides a six-fold cost improvement over prior art conventional memory.
BRIEF DESCRIPTION OF THE INVENTION
A data processing apparatus is described which comprises a microprocessor having data lines, address lines and control lines, a memory interface having input control lines, input address lines, output control lines, and output I/O lines wherein one or more input address lines of the memory interface are coupled to an equal number of address lines of the microprocessor. Further, a memory having control lines and I/O lines is provided, the control lines of the memory being coupled to output control lines of the memory interface, and I/O lines of the memory being coupled to output I/O lines of the memory interface. The memory receives command, data and address information through the I/O lines.
REFERENCES:
patent: 5603001 (1997-02-01), Sukegawa et al.
patent: 5812814 (1998-09-01), Sukegawa
Nguyen Than
Sierra Patent Group Ltd.
Sun Microsystems Inc.
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