Microprocessor that performs speculative tablewalks

Details Microprocessor that performs speculative tablewalks Microprocessor that performs speculative tablewalks

2011-08-09

2011-08-09

Nguyen, Than (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S205000

Reexamination Certificate

active

07996650

ABSTRACT:
A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address specified by a memory access instruction is missing in the TLB, performs operations of the tablewalk in an out-of-order manner with respect to the execution of unretired program instructions older than the memory access instruction while none of the predetermined set of conditions exists, and waits to perform the operations of the tablewalk until the microprocessor has retired all program instructions older than the memory access instruction when at least one of the predetermined set of conditions exists. The predetermined set of conditions may include the tablewalk needing to load information from a strongly-ordered page, update page mapping information, or access a global page.

REFERENCES:
patent: 5564111 (1996-10-01), Glew et al.
patent: 5613083 (1997-03-01), Glew et al.
patent: 1604055 (2005-04-01), None
Hu et al. “Out-of-Order Execution in Sequentially Consistent Shared Memory Systems: Principles.” Chinese J. Computers. vol. 20, No. 6. Jun. 1997. pp. 481-490.
“TLBs, Paging-Structure Caches, and Their Invalidation.” Application Note. Intel 317080-002 pp. 1-34.

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