Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2006-11-07
2006-11-07
Fleming, Fritz (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S238000
Reexamination Certificate
active
07134005
ABSTRACT:
A microprocessor caches in a branch target address cache (BTAC), for each of a plurality of previously executed branch instructions: a prediction of whether the branch instruction will be taken and is present in a cache line of instruction bytes provided by an instruction cache in response to a fetch address, a target address of the branch instruction, and a location of an opcode byte of the branch instruction within the cache line. The instruction cache provides the cache line to an instruction buffer and the BTAC provides the prediction, the target address, and the location in response to the fetch address. The microprocessor branches to the target address. A byte in the cache line within the instruction buffer indicated by the location provided by the BTAC is marked. An instruction decoder formats the instruction bytes in the cache line. The microprocessor erroneously branched to the target address if the instruction decoder indicates the marked byte is in a non-opcode location within one of the formatted instructions.
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Henry G. Glenn
McDonald Thomas C.
Parks Terry
Davis E. Alan
Fleming Fritz
Huffman James W.
IP-First LLC
Meonske Tonia L.
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