Microprocessor system with burstable, non-cacheable memory acces

Details Microprocessor system with burstable, non-cacheable memory acces Microprocessor system with burstable, non-cacheable memory acces

1996-12-18

2000-02-29

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711157, 711135, 395307, 39580034, 36518902, G06F 1200

Patent

active

06032225&

ABSTRACT:
A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected. According to a second embodiment of the invention, burst access to non-cacheable memory space (32) is acknowledged by the memory controller (60) by way of a burst acknowledge signal (BEN#) that is separate from the cache acknowledgment signal (KEN#).

REFERENCES:
patent: 5384906 (1995-01-01), Horst
patent: 5566324 (1996-10-01), Kass
patent: 5617556 (1997-04-01), Baumgartner et al.
patent: 5664148 (1997-09-01), Mulla et al.
patent: 5732241 (1998-03-01), Chan

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