Electronic digital logic circuitry – Function of and – or – nand – nor – or not
Reexamination Certificate
2007-04-17
2007-04-17
Le, Don (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
C326S008000
Reexamination Certificate
active
10182418
ABSTRACT:
A secure microprocessor is designed using quad-coded logic which is similar to dual-rail encoded asynchronous logic except that the ‘11’ state propagates an alarm. The alarm signal obliterates secure data in its path. Quad-coded logic provides resilience to power glitches and single-transistor or single-wire failures. The already low data dependency of the power consumption makes power analysis attacks difficult, and they are made even more difficult by inserting random delays in data and control paths, and by a set-random-carry instruction which enables software to make a non-deterministic choice between equivalent instruction sequences. These features are particularly easy to implement well in quad-coded logic.
REFERENCES:
patent: 4439835 (1984-03-01), Best et al.
patent: 4513389 (1985-04-01), Devchoudhury
patent: 4539682 (1985-09-01), Herman et al.
patent: 4783801 (1988-11-01), Kaule
patent: 4881199 (1989-11-01), Kowalski
patent: 4932053 (1990-06-01), Fruhauf et al.
patent: 5083106 (1992-01-01), Kostusiak et al.
patent: 5208489 (1993-05-01), Houston
patent: 5404402 (1995-04-01), Sprunk
patent: 5493240 (1996-02-01), Frank
patent: 2004/0228190 (2004-11-01), Kunemund et al.
patent: 2005/0141295 (2005-06-01), Laackmann
patent: 2005/0270061 (2005-12-01), Otterstedt
patent: 2005/0273631 (2005-12-01), Shu et al.
patent: 2333883 (1999-08-01), None
patent: 9963696 (1999-12-01), None
I. David et al., “An Efficient Implementation of Boolean Functions as Self-Timed Circuits,” IEEE Transactions on Computers, vol. 41, No. 1, pp. 2-11, 1992, no month.
R. Anderson et al., “Tamper Resistance—A Cautionary Note,” The Sec. USENIX Workshop on Electronic Commerce, Oakland, CA, Nov. 18-21, 1996; Proceedings pp. 1-11, ISBN 1-880446-83-9.
R. Anderson et al., “Low Cost Attacks on Tamper Resistant Devices,” in M. Lomas et al. (ed.): Security Protocols, 5thIntl. Workshop, Paris, France, Apr. 7-9, 1997, Proceedings, Springer LNCS v 1361, pp. 125-136, ISBN 3-540-64040-1.
S. Chari et al., “A Cautionary Note Regarding Evaluation of AES Candidates on Smart-Cards,” Sec. Ad. Encryption Standard Candidate Conf., Mar. 22-23, 1999, proceedings published by NIST, pp. 133-147.
P. Kocher, “Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems,” Adv. in Cryptology—Crypto 96, Aug. 18-22, 1996, Proceedings, Springer LNCS v 1109, pp. 104-113.
P. Kocher et al., “Differential Power Analysis,” Advances in Cryptology—Crypto 99, Proceedings Springer LNCS, 1999, no month.
O. Kömmerling et al., “Design Priniciples for Tamper-Resistant Smartcard Processors,” USENIX Workshop on Smartcard Technology, Chicago, IL, USA, May 10-11, 1999.
T. Messerges et al., “Investigations of Power Analysis Attacks on Smartcards,” Proceedings of USENIX Workshop on Smartcard Technology, May 1999, pp. 151-161.
Anderson Ross John
Moore Simon William
Dann Dorfman Herrell and Skillman, P.C.
Le Don
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