Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-02-20
2004-11-09
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S724000, C714S733000
Reexamination Certificate
active
06816983
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessors and, more particularly to a microprocessor internally provided with a test circuit.
2. Description of the Background Art
Referring to
FIG. 34
, a test circuit
111
for testing the operation of a microprocessor
101
is conventionally connected to microprocessor
101
directly or through an external bus
25
.
Microprocessor
101
includes: a memory
24
storing a program and various data; a processor core
22
executing the program stored in memory
24
; an external bus interface
26
serving as an interface portion with respect to external bus
25
; a processor bus
3
for interconnecting processor core
22
, memory
24
and external bus interface
26
; and an external event request signal input terminal
28
connected to test circuit
111
.
Test circuit
111
directly applies a test event signal
114
to microprocessor
101
for testing microprocessor
101
. Test event signal
114
is incorporated into microprocessor
101
from external event request signal input terminal
28
and applied to processor core
22
as an external event request signal
23
.
In the structure, data is set by a test program in processor core
22
to a control register (not shown) provided in test circuit
111
, so that test event signal
114
is controlled as shown in FIG.
35
.
Here, assume that test event signal
114
is in an assert state when it is “High.” An assert period of test event signal
114
is determined in synchronization with an operation cycle of test circuit
111
which is determined by operation frequencies of external bus
25
and test circuit
111
. Thus, the test program is controlled such that a test instruction
121
is executed with the operation cycle of processor core
22
in synchronization with that of test circuit
111
and that test event signal
114
is asserted at a desired timing.
However, it is difficult to explicitly specify the assert timing of test event signal
114
in a program when controlling the test program. Thus, the execution of the test program must be preliminary simulated.
In some cases, the execution cycle of test instruction
121
and the assert cycle of test event signal
114
are not in synchronization with each other. One example of such cases is related to a change in access time of processor core
22
with respect to an external device connected to external bus
25
or test circuit
111
. Another example of such cases is related to a change in pipeline control of processor core
22
. The execution cycle of instruction
122
executed in an operation cycle prior to the operation cycles of the elements to be tested may change, thereby resulting in the above mentioned problem. Therefore, the test program must be changed.
SUMMARY OF THE INVENTION
The present invention is made to solve the aforementioned program. An object of the present invention is to provide a microprocessor enabling a test to be performed without simulating a test program.
Another object of the present invention is to provide a microprocessor enabling a test to be performed without changing a program.
A microprocessor according to one aspect of the present invention includes: a processor core executing a program and outputting a program counter value of an instruction included in the program; and a test circuit outputting a test event signal in accordance with the program counter value. The test circuit includes: a PC (Program Counter) setting register holding a set program counter value; an output control register holding an output condition of the test event signal; a comparator connected to the processor core and PC setting register for comparing the program counter value output from the processor core and the program counter value set in the PC setting register; and a test event signal generating portion connected to the comparator and the output control register for generating the test event signal based on the comparison result obtained from the comparator and the output condition.
The test circuit and processor core operate in synchronization with the same clock signal, and a test event signal generated by the test circuit is applied to the processor core. Thus, an operator can readily specify an instruction to be executed in an assert period of the test event signal in a program. In addition, even if the access time of the processor core with respect to the memory or external device is changed, or the instruction execution time is changed due to the change in pipeline control of the processor core, a test can be performed without changing the program.
The test event signal is generated based on the output condition. Thus, the test event signal can be generated according to the purpose of a test.
Preferably, the microprocessor includes a plurality of test circuits, and a switch circuit connected to the plurality of test circuits and the processor core for switching among a plurality of test event signals output from the plurality of test circuits based on preliminary set connecting information for outputting it to the processor core.
If a value retained by the PC setting register or output control register is changed for every test circuit, test event signals based on various conditions can be generated. Thus, test event signals can be generated according to the purpose of a test.
More preferably, the output condition includes a count permitting condition indicating as to if a count operation is permitted in the assert period of the test event signal. The test circuit further includes a count value setting register holding a set count value. The test event signal generating portion includes a detector connected to the comparator, output control register and count value setting register for counting a period during which a comparison result from the comparator is a prescribed value in accordance with the count value held by the count value setting register when the count operation is permitted based on the count permitting condition and detecting the test event signal based on the count result.
The period during which the comparison result from the comparator is a prescribed value is counted and the test event signal is generated. Thus, during a loop process, the test event signal can also be asserted in a prescribed loop.
More preferably, the microprocessor further includes an external bus interface outputting a wait count value indicating a period before bus access on the external bus is permitted and externally connecting the microprocessor. The output condition includes a wait reference permitting condition indicating as to if reference to a wait count value is permitted in generating the test event signal. The test event signal generating portion includes a detector connected to the comparator, output control register and external bus interface for detecting an assert period of the test event signal when reference to the wait count value is permitted based on the wait reference permitting condition and when the wait count value output from the external bus interface is a prescribed value.
The test event signal can be asserted only in a period in which data access on the external bus is permitted. The test event signal is controlled in accordance with the wait count value. Thus, even if the access time of the processor core with respect to the external device is changed, the test event signal can be asserted only in a period when data access is permitted after the change in access time using a test program before the change in access time.
More preferably, the microprocessor further includes an external bus interface receiving a ready signal indicating that the bus access over the external bus is permitted and externally connecting the microprocessor. The output condition includes a ready signal reference permitting condition indicating as to if reference to the ready signal is permitted in generating the test event signal. The test event signal generating portion includes a detector connected to the comparator, output control register and external bus interface for d
Beausoliel Robert
McDermott Will & Emery LLP
Puente Emerson
Renesas Technology Corp.
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