Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-06-15
2003-09-23
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S005110, C712S205000, C712S227000
Reexamination Certificate
active
06625746
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to improving manufacturing yield for microprocessor chips by providing redundant, or spare instruction buffer entries and accurately identifying those entries which are available for use. More particularly, the present invention includes a technique that tests the instruction buffer circuitry and stores the results of these tests in order to ensure that a sufficient number of buffer entries are available to meet the baseline specification of the microprocessor.
2. Description of Related Art
With the continual advance of computer technology, more and more circuitry is being provided on each integrated circuit (IC), which makes them correspondingly more complex. These chips are likely to include millions of transistors and be quite large. It is not surprising that the cost to fabricate these ICs is relatively high and, as the cost increases, the manufacturing yield becomes critical in order for producers of these chips to remain competitive.
Manufacturing yield is essentially the percentage of ICs that meet the design specification relative to the total number of chips produced. Of course, as chip complexity and size increases, the manufacturing yield usually decreases. Further, after a new IC design has been manufactured for a significant period of time, per chip costs often decrease as the fabrication process is tuned and optimized. Thus, in order to stay competitive it is often necessary, if not critical, to increase manufacturing yields especially during the early stages of chip production when the manufacturing costs are highest.
It can be seen that yield on large chips is an important issue and techniques for tolerating small numbers of random defects in the manufacturing process are increasingly more important. While redundancy in caches has been used for some time, it has not been used for other structures in microprocessors. In particular, redundancy has not been used in the microprocessor register file circuitry that is common in microprocessors and whose area contribution in terms of chip real estate is growing. More particularly, the contribution of the register file and instruction buffer to the overall core area of modern microprocessors is increasing to the point where both of these structures can make up approximately ten percent (10%) of the microprocessor core for a total of about 20% of the core area and core functionality. This illustrates the importance in terms of complexity and size of just two microprocessor core structures where redundancy can be used in accordance with the present invention to improve performance.
Modem microprocessors capable of out-of-order execution make use of large numbers of dataflow-oriented instruction buffers for holding instructions while their operands develop. The instruction buffers accept new instructions from the dispatch logic, and coordinate the issue of instructions to various execution units based on operand availability, instruction age and other mechanisms. Typically, these instruction buffers contain content addressable memory (CAM) oriented circuitry that detects when required operand values are available, and either captures a copy of the operand data or sets a flag to indicate that the data is not available in subsequent stages of the execution pipeline (i.e. in a register file that will be accessed as the instruction is allowed to progress).
In general, as instructions are provided to the instruction buffer, they are allocated into unused entries. That is, each entry is the same as every other entry such that a particular instruction can be allocated to any entry in the instruction buffer. However, sometimes, due to limitations in the instruction issue policy, it may be advantageous to allocate new instructions into unused entries that are as close to the “physical bottom” of the instruction buffer stack as possible. Typically, the instruction buffers are “self allocating”, i.e. the instruction is presented to the group of instruction buffer entries and the dataflow-oriented logic surrounding the entries automatically coordinates which of the available entries will receive the instruction. Further, instructions leave the instruction buffer as their dependencies are resolved (independent of their position in the buffer or age) and are “issued” to an execution unit (actually, it is common practice to allow them to linger in the instruction buffer entry for a fixed number of cycles beyond the issue point so that if the instruction is “rejected”, it can easily be reissued without having to be re-fetched and re-dispatched).
Dataflow instruction processing as used herein refers to a microprocessor technology wherein resolution of the dependencies associated with the instruction being executed occurs in a continuous manner with a reduced need for pipeline stages, as commonly used in microprocessor technologies. Generally, logic is provided which corresponds to an individual instruction being processed, rather than a functional pipeline stage. In other words, instruction processing focuses more on the individual instruction than a particular pipeline stage. Of course, it should be noted that the scope of the present invention contemplates all types of microprocessors, microcontrollers, embedded controllers, digital signal processors and the like including those having distinct pipeline stages.
In a microprocessor with renamed registers, the machine automatically maps the architecturally defined set of “logical registers” into a larger set of “physical registers” to avoid various types of false dependencies and to allow easy purging or speculative results when necessary. As instructions are processed and registers are needed, register allocation/deallocation logic examines the state of the physical register pool, and selects a register that is currently not active, and then marks it as “in use”. Later, when the instruction is either completed (or purged), the register deallocation logic frees the register again for future use.
More particularly, most modern microprocessors use rename buffers, or registers. It should be noted that the terms “rename registers” and “rename buffers” will be used interchangeably herein. These rename buffers act as temporary storage for instructions that have not completed and as write-back buffers for those that have. To avoid contention for a given register location rename registers are provided for storing instruction results before they are completed and committed to the architected registers. For example, a certain microprocessor may include thirty-two, thirty-two bit general purpose registers (GPRs) which are considered architected registers and twelve, thirty-two bit rename registers for holding results prior to their commitment to the architected registers. Further, rename registers may also be provided for other architected registers, such as two rename buffers for the floating point registers (FPR) and eight rename registers for the condition register (CR).
Generally, when the dispatch unit provides an instruction to the appropriate execution unit (i.e. the integer unit (IU), floating point unit (FPU), load/store unit (L/S), or the like), it allocates a rename register for the results of that instruction. The dispatch unit also provides a tag to the execution unit identifying the result that should be used as the operand. When the proper result is returned to the rename buffer it is provided to the execution unit, which begins execution of the instruction. Instruction results are not transferred from the rename registers to the architected registers until any speculative branch conditions are resolved and the instruction itself is retired without exceptions. If a speculatively executed branch is found to have been incorrectly predicted, the speculatively executed instructions following the branch are flushed and the results of those instructions are flushed from the rename registers.
As an example, conventional microprocessors avoid contention for a given register file location and in the course of
Beausoliel Robert
McBurney Mark E.
Wilson Yolanda L.
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