Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Patent
1996-01-31
2000-01-04
Ellis, Richard L.
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
712203, G06F 9302
Patent
active
060121394
ABSTRACT:
A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.
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Biswas Prasenjit
Kawasaki Shumpei
Nakagawa Norio
Nishii Osamu
Uchiyama Kunio
Ellis Richard L.
Hitachi Micro Systems Inc.
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