Microprocessor including controller for reduced power...

Details Microprocessor including controller for reduced power... Microprocessor including controller for reduced power...

1998-08-03

2001-05-22

Lefkowitz, Sumati (Department: 2181)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C712S208000, C712S245000

Reexamination Certificate

active

06237101

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a microprocessor, and more particularly to a microprocessor including a controller in which alternating current (AC) power is reduced as a function of a sequential machine, and a method therefor.
2. Description of the Related Art
Mobile computers (e.g., portable personal computers such as IBM's ThinkPad®), communications devices (e.g., portable, cellular telephone, selective call receiving device (pager) etc.), and other portable device (e.g., “smart” cards, etc.) must be designed for very low power operation and consumption to conserve the limited charge of a battery incorporated into the respective devices. Thus, every operation must minimize the power use for maximum battery life.
Two power components which are candidates for reducing power are the alternating current (AC) power, and the standby power. A primary method of driving the AC power has been through using low-power circuits, and improved technology enabling lower VDD. The standby power has been the primary focus from a logic design and architecture standpoint. The conventional methods have involved different methods of shutting down logic whenever the product is in the standby power mode. Thus, through technology advances and standby shutdown, some power savings have been achieved.
However, a third area of power consumption is the reduction of power while the processor (e.g., microprocessor) is running code (e.g., application code). This area of power reduction has not been addressed as an area of power savings, as frequently as the other two approaches described above.
This area of power reduction is a function of logic gates in the microprocessor making transitions from low to high values (e.g., “0” to “1”), or high to low values (e.g., typically called “node toggle”), so as to render a binary value. Conventional analysis techniques have attempted to minimize node toggle by function. Hence, if an “add” subroutine is to be performed, the add is attempted with the minimum amount of toggle. Specifically, to minimize the amount of toggle, the conventional technique selects an adder-type (e.g., a ripple adder, carry adder, etc.) to be employed which would minimize the transitions to get the result.
Within the microprocessor, control signals control the actual processing in the microprocessor. For example, these signals are carried on control lines which may activate parallel conductors (e.g., buses) so that data placed on them will flow to the proper destination. The control lines supervise the order which microinstructions are performed after the opcode has been decoded by logic circuitry. Using clock inputs, the control circuitry maintains the proper sequence of the processing task. The control signals enable the various device functions which can be active high or active low.
However, a problem with the conventional approach is that from cycle to cycle, the control signals are not linked (e.g., examined in relation to one another). Hence, the control signals do not “look backward” to a previous cycle's function, but instead the control signals are treated independently. For example, if a previous cycle is an “ADD” instruction, and the next cycle is a “MULT” instruction, then each opcode (e.g., operation code instruction in binary representation) will have its own specific control signals (e.g., control signals designating an “ADD” and separate, different control signals designating the “MULT”). Typically, there will be a defined state (e.g., a “0” or “1” state) for every control signal for every opcode. Thus, a binary representation is provided of the control signal to execute the control signal's particular function. These states are not defined by the prior opcode, but strictly from the executing opcode (e.g., the opcode's function).
Two common techniques for decoding are distributed decode and microcode.
Referring to
FIG. 1
, the distributed decode approach is where each logic signal is derived in a section of logic description completely. Specifically, in
FIG. 1
, random logic gates are shown (e.g., the gates may be AND, OR, etc. gates). Each of the random logic gates issues an individual signal.
Thus, in a design unit employing the distributed approach, each logic signal is derived in a section of logic description completely. The design unit becomes a series of individual decodes of control signals in which the sum total of the individual decodes represents the opcode's function. This approach is advantageous since, for each control function, a relatively small amount of code can be written that represents that opcode's function. Thus,
FIG. 1
illustrates the conventional splintered, random decode of instructions.
However, with this approach, it is difficult to read/debug any one opcode function, since the function is spread out over a very large design unit. Further, it is difficult to perform engineering change (EC) and to view the entire opcode function.
An alternative conventional approach is a microcode approach which is shown in FIG.
2
. In the microcode approach, a system
20
is provided in which each opcode is translated from an entry point address (e.g., instruction register (IR)
21
) to a microcode read-only memory (ROM)
22
(or to a programmable logic array (PLA) (not shown)). A complete set of control signals
23
is output from the ROM
22
/Programmable logic array (PLA). The control signals of the set typically are output simultaneously.
Hence, for every opcode, one set of control signals is available. This feature enables the designer to perform the engineering change (EC) function quickly since only the control signals need be edited at a localized address which represents that opcode. Thus, the microcode approach is easier to read and to define opcodes.
The disadvantages of the microcode approach include that there is no flexibility (e.g., only a fixed value of “0” or “1” is provided), it has a limited function, and is relatively slow as compared to the distributed approach.
Thus, both of these approaches have disadvantages and neither approach optimizes performance and utility of the system.
Hence, currently, there is no means or method of knowing all possible opcode combinations, and then, based upon this knowledge, selecting the next state to minimize the next cycle power but yet without impacting the cycle's function. Instead, the conventional techniques perform a full ON/full OFF from one cycle to the next, thereby consuming much power.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional methods and structures, an object of the present invention is to provide a method and structure for reducing AC power by deriving the next cycle's control signals based on the next cycle's function along with the previous cycle state.
Specifically, the present inventors have discovered that large unnecessary node toggle swings can occur based on what is in the pipeline last (e.g., the previous cycle's function), and what is in the pipeline next (e.g., the next cycle's function).
In one aspect of the present invention, a microprocessor is provided which includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions.
Preferably, the microcode unit includes an instruction address input for receiving an instruction address, a control variable input for receiving a control variable corresponding to a current state of the microprocessor, a control signal input for receiving all the control signals output by the microcode unit for an immediately preceding instruction, and a plurality of embedded logic circuits each dedicated for evaluating one unique type of instruction received by the microcode unit.
In another aspect of the present invention, a method of updating a design of a semiconductor chip at a hardware design language level (HDL) of simulation, to maximize an amount of logic that can be set to a previous cycle s

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