Microprocessor including bank-pipelined cache with...

Details Microprocessor including bank-pipelined cache with... Microprocessor including bank-pipelined cache with...

2006-10-17

2006-10-17

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S118000, C711S131000, C711S144000

Reexamination Certificate

active

07124236

ABSTRACT:
A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a plurality of storage blocks, each configured to store a plurality of data units. Each of the plurality of storage blocks may be accessed asynchronously. In addition, the cache subsystem includes a plurality of tag units which are coupled to the plurality of storage blocks. Each of the tag units may be configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within the plurality of storage blocks. Each of the plurality of tag units may be accessed synchronously.

REFERENCES:
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patent: 5860081 (1999-01-01), Herring et al.
patent: 6108755 (2000-08-01), Kabemoto et al.
patent: 6237064 (2001-05-01), Kumar et al.
patent: 6427191 (2002-07-01), Fu et al.
patent: 6574708 (2003-06-01), Hayter et al.

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