Microprocessor including an efficient implementation of extreme

Details Microprocessor including an efficient implementation of extreme Microprocessor including an efficient implementation of extreme

1997-10-10

2000-02-22

Eng, David Y.

Electrical computers and digital processing systems: processing

Processing control

Logic operation instruction processing

G06F 9305

Patent

active

06029244&

ABSTRACT:
An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an output of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In another embodiment, a similar execution unit is provided which handles vector operands.

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IBM Technical Disclosure, "ALU Implementing Hative Miniumum/Maximum Functioin For Signal Processing Applications," vol. 29, No. 5, Oct. 1986.
English language abstract as downloaded and printed from Dialog Website for EPO0678808A1, 1 page, from priority application date Apr. 17, 1995.

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