Microprocessor idle mode management system

Details Microprocessor idle mode management system Microprocessor idle mode management system

2007-05-22

2007-05-22

Elamin, A S (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000, C713S321000, C713S002000, C713S324000, C710S260000, C710S261000, C710S262000, C710S263000, C710S264000, C710S265000, C710S267000, C710S268000, C710S269000

Reexamination Certificate

active

10358181

ABSTRACT:
An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.

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