Microprocessor having ROM areas emulated by RAM areas

Details Microprocessor having ROM areas emulated by RAM areas Microprocessor having ROM areas emulated by RAM areas

1999-04-19

2001-10-16

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S102000, C711S104000, C711S173000, C703S024000

Reexamination Certificate

active

06304950

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer having a ROM emulation function used for debugging software.
2. Description of the Prior Art
Referring now to
FIG. 10
, there is illustrated a diagram showing a concept underlying a prior art microcomputer as disclosed in, for example, “Mitsubishi 32-bit RISC single-chip microcomputer M32R family M32R/E series 32160 group M32160F3UFP M32160F4UFP User Manual”, pp.5-37 to 5-39, Mitsubishi Electric Corp. and Mitsubishi Semiconductor System Corp., Aug. 20, 1998. In the figure, reference numeral
1
denotes a read-only-memory or ROM,
2
denotes a random-access-memory or RAM,
11
denotes each of a plurality of ROM areas into which the ROM
1
is divided, each ROM area having a predetermined size, e.g., 8Kbytes as shown in the figure, and
21
denotes a first RAM area in the RAM
2
having a predetermined size, e.g., 8Kbytes as shown in the figure, which is the same as that of each ROM area
11
. Each ROM area
11
includes a starting address specifying the memory location of its top, such as address A, B, or the like as shown in FIG.
10
.
In operation, when changing the current mode into ROM simulation mode, the starting address specifying the ROM area
11
that is to be replaced with the first RAM area
21
, for example, the address A is set, and “1” is written into an emulation mode bit of a control register not shown. When the emulation mode bit is set to “1”, the ROM area
11
whose starting address has been specified, in this case, whose starting address is the address A, can be replaced with the first 8KB RAM area
21
. Therefore, when the ROM area
11
whose address has been selected in the ROM emulation mode, in this case, is the address A, is accessed by something, the first RAM area
21
on the RAM
2
is actually accessed.
When performing an emulation operation on another ROM area
11
, for example, the next ROM area
11
whose starting address is the address B, the same process is carried out by setting another address specifying the memory location of the top of the other ROM area, for example, the address B. The ROM area
11
whose starting address has been specified, for example, whose starting address is the address B, is replaced with the first 8KB RAM area
21
. Therefore, when the ROM area
11
whose address has been specified in the ROM emulation mode is accessed by something, for example, when the ROM area
11
with the starting address B is accessed by something, the first RAM area
21
in the RAM
2
is actually accessed. In this manner, an application that needs to change data while it is running can dynamically change the data using the first RAM area
21
on the RAM
2
.
Japanese Patent Application publications (KOKAI) No. 62-251934, No. 64-84341, No. 7-302254, and No. 6-139102 disclose a prior art technique that relates to a microcomputer having such a ROM emulation function, for example.
A problem with such a prior art microcomputer so constructed as mentioned above is that since one of the plurality of ROM area
11
in the ROM
1
is securely replaced with a predetermined RAM area
21
in the RAM
2
in the emulation
30
mode, the memory map of part of the RAM in which the program that is debugged and tuned in the emulation mode is stored differs from that of corresponding part of the ROM in which the program is actually stored, and therefore, the whole of the program needs to be reconfigured (or rewritten) after the tuning is complete.
SUMMARY OF THE INVENTION
The present invention is made to overcome the above problem. It is therefore an object of the present invention to provide a microcomputer capable of finely tuning any program on a ROM without having to reconfigure the whole of the program after the tuning is complete.
In accordance with one aspect of the present invention, there is provided a microcomputer including a ROM and a RAM built therein, comprising: a plurality of ROM areas formed on the ROM, on each of which emulation can be performed; a plurality of RAM areas formed on the RAM; an assigning unit for assigning at least one RAM area to each of the plurality of ROM areas; and a replacing unit for replacing each of the plurality of ROM areas with a corresponding RAM area assigned to each of the plurality of ROM areas.
In accordance with a preferred embodiment of the present invention, the plurality of ROM areas on each of which emulation can be performed are equal in size (or storage amount), and the plurality of RAM areas that can be respectively replaced with the plurality of ROM areas have the same size as the plurality of ROM areas.
In accordance with another preferred embodiment of the present invention, the assigning unit includes a plurality of ROM area specification registers respectively associated with the plurality of RAM areas on the RAM, each for specifying one ROM area that is to be replaced with a corresponding RAM area associated with each of the plurality of ROM area specification registers. In addition, the replacing unit can replace one ROM area, which is specified by each of the plurality of ROM area specification registers, with a corresponding one of the plurality of RAM areas on the RAM that is associated with each of the plurality of ROM area specification registers.
In accordance with another preferred embodiment of the present invention, each of the plurality of ROM area specification registers includes a ROM area specification section for specifying one ROM area that is to be replaced with a corresponding one of the plurality of RAM areas on the RAM that is associated with each of the plurality of ROM area specification registers, and an enable bit for enabling or disabling replacement of the ROM area specified by the ROM area specifying section with the corresponding RAM area.
In accordance with another preferred embodiment of the present invention, the microcomputer further comprises a plurality of switches respectively associated with the plurality of RAM areas, each for connecting or disconnecting a corresponding one of the plurality of RAM areas with or from one ROM area associated with the corresponding RAM area, according to a control signal applied to an external terminal. Each of the plurality of switches is closed or opened to enable or disable replacement of one ROM area with a corresponding one of the plurality of RAM areas associated with each of the plurality of switches.
In accordance with another preferred embodiment of the present invention, each of the plurality of ROM areas has an arbitrary size and a corresponding one of the plurality of RAM areas that is to be replaced with each of the plurality of ROM areas has the same size as each of the plurality of ROM areas. In addition, the assigning unit includes a plurality of ROM area specification registers respectively associated with the plurality of RAM areas on the RAM, each for storing a starting address and an ending address for specifying one ROM area that is to be replaced with each of the plurality of RAM areas associated with each of the plurality of ROM area specification register.
In accordance with another preferred embodiment of the present invention, the microcomputer further comprises a selection unit for, when the assigning unit sets information indicating an identical ROM area to two or more ones of the plurality of ROM area specification registers, selecting one RAM area from among two or more RAM areas associated with the two or more ROM area specification registers specifying the same ROM area according to priorities assigned to the two or more RAM areas, and a switching unit for connecting only the selected RAM area with the identical ROM area so as to enable replacement of the identical ROM area with the selected RAM area.
In accordance with another preferred embodiment of the present invention, the microcomputer further comprises an emulation mode enable register for storing information for enabling or disabling an overall emulation function using the RAM, a gate array for passing the contents of the enable bit of eac

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