Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-10-01
2003-04-22
Bragdon, Reginald G. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S205000, C711S209000, C711S210000
Reexamination Certificate
active
06553460
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to microprocessor and similar computing-type devices, and more particularly to microprocessors and similar computing-type devices with improved memory management and cache capabilities, particularly those that include virtual cache memories.
BACKGROUND OF THE INVENTION
Microprocessors, data processors, microcomputers, microcontrollers and other computing-type devices (herein generally referred to simply as “microprocessors”) often are implemented to include a memory management units (MMU) and one or more cache memories. As is known in the art, the MMU typically improve microprocessor capabilities by managing the separation of logical or virtual address space (virtual memory) from physical address space (main memory), and often includes a translation lookaside buffer (TLB) or other resources to translate between logical and physical addresses. Also as is known in the art, a cache memory maintains a copy of the contents of the most recently accessed memory locations and is able to provide the data to the processor very quickly should any address in the cache be accessed again.
Caches generally are divided into three types: (1) physically indexed physically tagged (PIPT); (2) virtually indexed physically tagged (VIPT); and (3) virtually indexed virtually tagged (VIVT) or “virtual cache”. The most commonly used cache configuration is the VIPT cache. In VIPT caches, the virtual address is used to select the index into the cache. The physical tag is then compared with part of the physical address, which is derived from the physical page number (PPN) and size information provided by the TLB. Virtual caches index into the cache using the virtual address (similar to VIPT caches), but the tag residing in the cache is also virtual. In case of a virtual tag match, the data is immediately returned without any TLB access. For this reason, virtual caches tend to have faster cache access times as compared to VIPT caches. Therefore, it often is possible to achieve higher frequencies with a virtual cache.
While the use of such virtual caches has been proposed (see U.S. Pat. No. 5,930,833, which is incorporated herein by reference), there are a number of issues that may arise. For example, virtual caches have very fast access time since they do not incur delays during the virtual-physical address translation. They do incur, however, tend to incur a consistency problem, often called the synonym problem. This is caused when two different virtual addresses point to a unique physical address, or the same virtual addresses with different process ID's point to a unique physical address. While U.S. Pat. No. 5,930,833 proposed certain strategies for dealing with the synonym problem and for otherwise improving microprocessors, the need exists for yet further improvements in microprocessors incorporating MMUs, TLBs, caches, virtual caches, etc.
SUMMARY OF THE INVENTION
The present invention provides microprocessors, and methods of operating microprocessors, utilizing improved MMUs, TLBs, caches and virtual caches. In accordance with the present invention, MMUs may be provided in a manner that the MMU may more readily be scaled to accommodate the development of later generation microprocessors. MMU resources preferably are accessed in a configuration register space separate from the physical and logical address spaces, and such MMU configuration registers are implemented in a manner to more readily accommodate future, scaled versions. Instructions to access, modify and control the MMU configuration register contents preferably are provided.
MMUs in accordance with preferred embodiments also provide particular linked behavior with the cache or virtual cache. In such preferred embodiments, the cache or virtual cache preferably is frozen and bypassed when the MMU is disabled, although certain instructions may yet access the cache configuration registers (the cache sources preferably also are accessed in the separate configuration register space).
MMUs in accordance with certain preferred embodiments also operate in a more optimal manner with virtual cache memories. As one illustrate example, permissions may be widened in the cache upon finding that the permission in the MMU/TLB is wider that the corresponding entry in the cache, and desirably the cache permission may automatically be widened.
Also in accordance with the present invention, the cache as well as the MMU may be provided in a manner to be more readily scalable to accommodate the development of later generation microprocessors. Cache resources also preferably are accessed in a configuration register space separate from the physical and logical address spaces, and such cache configuration registers are implemented in a manner to more readily accommodate future, scaled versions. Instructions to access, modify and control the cache configuration register contents preferably are provided.
In accordance with preferred embodiments, the MMU and cache is implemented in a manner to more readily enable versions with virtual and non-virtual cache designs.
In order to more optimally operate caches, microprocessors with caches, instructions are provided to enable cache locking and cache invalidate/flush/purge operation in a more desirable manner. In general, in accordance with the present invention, caches and in particular virtual caches may more be readily implemented, managed and controlled using configuration registers, cache control instructions and other implements as more described below.
Accordingly, the objects of the present invention include the provision of microprocessors having MMUs/TLBs/caches and/or virtual caches with the foregoing advantages and benefits, and as well as the advantages and benefits as will be disclosed in, and/or apparent from, the detailed description to be hereinafter set forth.
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Chopra Rajesh
Debbage Mark
Yoshioka Shin-ichi
Bragdon Reginald G.
Elmore Stephen
Hitachi , Ltd.
Loudermilk & Associates
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