Microprocessor having a page prefetch cache for database...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S156000, C711S128000

Reexamination Certificate

active

06848028

ABSTRACT:
A microprocessor cache configuration for reducing database cache misses and improving the processing speed, comprising a level-1 data cache, and a page prefetch cache. The page prefetch cache is adjacent the level-1 data cache. The page prefetch cache is configured to receive and store one or more database pages. Additionally, a page prefetch instruction provides the database pages to the page prefetch cache. The page prefetch instructions are generated by a compiler or by developer software.

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Compiler driven data cache prefetching for high performance computers. Chi-Hung Chi; Kam-Kong Fang. Tencon '94. IEEE Region 10's Ninth Annual International Conference. 1994. Page(s): 274-278 vol. 1.

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