Microprocessor having a CPU and at least two memory cell arrays

Details Microprocessor having a CPU and at least two memory cell arrays Microprocessor having a CPU and at least two memory cell arrays

1997-04-29

1999-11-09

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 28, 395527, 36518525, 365222, 36523003, 711106, G06F 1100, G06F 9455, G11C 1606, G11C 800

Patent

active

059833670

ABSTRACT:
A CPU can selectively execute a normal processing mode and a debugging mode on the basis of a control signal sent from a control unit. A first memory cell array is accessed in the normal processing mode, and a second memory cell array is accessed in the debugging mode. A sense amplifier and a bit line are shared by the first and second memory cell arrays. Consequently, it is possible to relieve an increase in the area of the semiconductor chip caused by existence of the two memory cell arrays. That is, an area of a semiconductor chip is reduced. A spare memory cell array may be provided for compensating for a defective cell of the first memory cell array. A refresh circuit may be provided for refreshing the first and second memory cell arrays.

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patent: 5872737 (1999-02-01), Tsuruda et al.
patent: 5877780 (1999-03-01), Lu et al.
Stanley Burns and Paul Bond, Principles of Electronic Circuits: 2nd Edition, p. 751, 1997.

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